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Updated the caravan netlist and implemented the caravan testbench.

This commit is contained in:
Tim Edwards 2021-10-25 15:08:13 -04:00
parent a7fec91c4c
commit bc9944ce20
8 changed files with 1360 additions and 471 deletions
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35
verilog/dv/caravel/mgmt_soc/Makefile Normal file
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
# ---- Test patterns for project striVe ----
.SUFFIXES:
.SILENT: clean all
PATTERNS = gpio_mgmt gpio mem uart perf hkspi sysctrl mprj_ctrl mprj_bitbang pass_thru timer timer2 pll storage qspi caravan irq user_pass_thru spi_master
all: ${PATTERNS}
for i in ${PATTERNS}; do \
( cd $$i && SIM=RTL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
( cd $$i && SIM=GL make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
done
clean: ${PATTERNS}
for i in ${PATTERNS}; do \
( cd $$i && make clean ) ; \
done
.PHONY: clean all

86
verilog/dv/caravel/mgmt_soc/caravan/Makefile Normal file
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
PDK_PATH = $(PDK_ROOT)/sky130A
VERILOG_PATH = ../../../..
RTL_PATH = $(VERILOG_PATH)/rtl
BEHAVIOURAL_MODELS = ../../
# Temporary: Path to management SoC wrapper repository
MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
FIRMWARE_PATH = ../..
GCC_PATH?=/ef/apps/bin
GCC_PREFIX?=riscv32-unknown-elf
SIM_DEFINES = -DFUNCTIONAL -DSIM
SIM?=RTL
.SUFFIXES:
PATTERN = caravan
all: ${PATTERN:=.vcd}
hex: ${PATTERN:=.hex}
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
$< -o $@
else
iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
$< -o $@
endif
%.vcd: %.vvp
vvp $<
%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
%.hex: %.elf
${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
# to fix flash base address
sed -i 's/@10000000/@00000000/g' $@
%.bin: %.elf
${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
check-env:
ifndef PDK_ROOT
$(error PDK_ROOT is undefined, please export it before running make)
endif
ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
endif
ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
endif
# check for efabless style installation
ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
endif
# ---- Clean ----
clean:
rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
.PHONY: clean hex all

27
verilog/dv/caravel/mgmt_soc/caravan/README Normal file
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<!---
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
-->
------------------------------------------------
Caravan
basic testbench
------------------------------------------------
This testbench exercises the basic use of the Caravan analog project
harness, which is equivalent to the Caravel chip with 11 GPIOs
removed from the top of the padframe and replaced with straight-through
connections to pads.

127
verilog/dv/caravel/mgmt_soc/caravan/caravan.c Normal file
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/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include "../../defs.h"
// --------------------------------------------------------
/*
* Caravan GPIO Test
*
* This is mainly a test of the digital I/O surrounding the analog
* pinouts on the caravan chip to make sure that they are connected
* properly after the middle GPIO pads and serial loader blocks are
* clipped out from the caravel design.
*
* Tests PU and PD on the lower 8 pins while being driven from outside
* Tests Writing to the upper 8 pins
* Tests reading from the lower 8 pins
*/
void main()
{
int i;
/* Set data out to zero */
reg_mprj_datal = 0;
/* GPIO 14 to 24 have been replaced by analog and should be set */
/* to mode output to keep the input from floating. */
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Lower 8 pins are input and upper 8 pins are output */
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
// change the pull up and pull down (checked by the TB)
reg_mprj_datal = 0xa0000000;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_mprj_datal = 0x0a000000;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
// read the lower 8 pins, add 1 then output the result
// checked by the TB
reg_mprj_datal = 0xaa000000;
while (1) {
int x = (reg_mprj_datal & 0x3f80) >> 7;
reg_mprj_datal = (x+1) << 25;
}
}

214
verilog/dv/caravel/mgmt_soc/caravan/caravan_tb.v Normal file
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`default_nettype none
/*
* SPDX-FileCopyrightText: 2017 Clifford Wolf, 2018 Tim Edwards
*
* StriVe - A full example SoC using PicoRV32 in SkyWater s8
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
* Copyright (C) 2018 Tim Edwards <tim@efabless.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* SPDX-License-Identifier: ISC
*/
`timescale 1 ns / 1 ps
`include "__uprj_analog_netlists.v"
`include "caravan_netlists.v"
`include "spiflash.v"
module caravan_tb;
reg clock;
reg power1;
reg power2;
always #10 clock <= (clock === 1'b0);
initial begin
clock <= 0;
end
initial begin
$dumpfile("caravan.vcd");
$dumpvars(0, caravan_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (25) begin
repeat (1000) @(posedge clock);
$display("+1000 cycles");
end
$display("%c[1;31m",27);
`ifdef GL
$display ("Monitor: Timeout, Test GPIO (GL) Failed");
`else
$display ("Monitor: Timeout, Test GPIO (RTL) Failed");
`endif
$display("%c[0m",27);
$finish;
end
wire [37:0] mprj_io; // Most of these are no-connects
wire [6:0] checkbits_hi; // Upper 7 valid GPIO bits
wire [7:0] checkbits_lo; // Lower 6 valid GPIO bits (read)
reg [7:0] setbits_lo; // Lower 6 valid GPIO bits (write)
assign mprj_io[13:7] = setbits_lo;
assign checkbits_lo = mprj_io[13:7];
assign checkbits_hi = mprj_io[31:25];
assign mprj_io[3] = 1'b1; // Force CSB high.
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire gpio;
reg RSTB;
// Transactor
initial begin
setbits_lo <= {7{1'bz}};
wait(checkbits_hi == 7'h50);
repeat (500) @(posedge clock);
setbits_lo <= 7'h30;
wait(checkbits_hi == 7'h05);
repeat (500) @(posedge clock);
setbits_lo <= 7'h0f;
wait(checkbits_hi == 7'h55);
repeat (1000) @(posedge clock);
setbits_lo <= 7'h00;
repeat (1300) @(posedge clock);
setbits_lo <= 7'h01;
repeat (1300) @(posedge clock);
setbits_lo <= 7'h03;
end
// Monitor
initial begin
wait(checkbits_hi == 7'h50); // 1st pull test
`ifdef GL
$display("Monitor: Test GPIO (GL) Started");
`else
$display("Monitor: Test GPIO (RTL) Started");
`endif
wait(checkbits_lo == 7'h30); // (1st pull test result)
$display("Monitor: Check 1 seen");
wait(checkbits_hi == 7'h05); // 2nd pull test
$display("Monitor: Check 2 seen");
wait(checkbits_lo == 7'h0F); // (2nd pull test result)
$display("Monitor: Check 3 seen");
wait(checkbits_hi == 7'h55); // loopback test
$display("Monitor: Check 4 seen");
wait(checkbits_lo == 7'h00); // 1st value set
$display("Monitor: Check 5 seen");
wait(checkbits_hi == 7'h01); // 1st loopback read
$display("Monitor: Check 6 seen");
wait(checkbits_lo == 7'h01); // 2nd value set
$display("Monitor: Check 7 seen");
wait(checkbits_hi == 7'h02); // 2nd loopback read
$display("Monitor: Check 8 seen");
wait(checkbits_lo == 7'h03); // 3rd value set
$display("Monitor: Check 9 seen");
wait(checkbits_hi == 7'h04); // 3rd loopback read
`ifdef GL
$display("Monitor: Test GPIO (GL) Passed");
`else
$display("Monitor: Test GPIO (RTL) Passed");
`endif
$finish;
end
initial begin
RSTB <= 1'b0;
#1000;
RSTB <= 1'b1; // Release reset
#2000;
end
initial begin // Power-up
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
always @(mprj_io) begin
#1 $display("GPIO state = %b (%d - %d)", mprj_io,
checkbits_hi, checkbits_lo);
end
wire VDD3V3;
wire VDD1V8;
wire VSS;
assign VDD3V3 = power1;
assign VDD1V8 = power2;
assign VSS = 1'b0;
// These are the mappings of mprj_io GPIO pads that are set to
// specific functions on startup:
//
// JTAG = mgmt_gpio_io[0] (inout)
// SDO = mgmt_gpio_io[1] (output)
// SDI = mgmt_gpio_io[2] (input)
// CSB = mgmt_gpio_io[3] (input)
// SCK = mgmt_gpio_io[4] (input)
// ser_rx = mgmt_gpio_io[5] (input)
// ser_tx = mgmt_gpio_io[6] (output)
// irq = mgmt_gpio_io[7] (input)
caravan uut (
.vddio (VDD3V3),
.vssio (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("caravan.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
`default_nettype wire

1221
verilog/rtl/caravan.v
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56
verilog/rtl/caravan_netlists.v
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@ -20,12 +20,12 @@
`ifdef SIM
`include "defines.v"
`include "user_defines.v"
`include "pads.v"
`include "defines.v"
`include "user_defines.v"
`include "pads.v"
/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
`ifdef EF_STYLE // efabless style pdk installation; mainly for open galaxy users
/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
`ifdef EF_STYLE // efabless style pdk installation; mainly for open galaxy users
`include "libs.ref/verilog/sky130_fd_io/sky130_fd_io.v"
`include "libs.ref/verilog/sky130_fd_io/sky130_ef_io.v"
`include "libs.ref/verilog/sky130_fd_io/sky130_ef_io__gpiov2_pad_wrapped.v"
@ -35,7 +35,7 @@
`include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
`include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
`include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
`else
`else
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v"
@ -45,11 +45,12 @@
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
`endif
`endif
`ifdef GL
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
`ifdef GL
// Assume default net type to be wire because GL netlists don't have the wire
// definitions
`default_nettype wire
`include "gl/mgmt_core.v"
`include "gl/digital_pll.v"
`include "gl/DFFRAM.v"
@ -57,40 +58,35 @@
`include "gl/user_id_programming.v"
`include "gl/chip_io_alt.v"
`include "gl/mprj_logic_high.v"
`include "gl/mprj2_logic_high.v"
`include "gl/mprj2_logic_high.v"
`include "gl/mgmt_protect.v"
`include "gl/mgmt_protect_hv.v"
`include "gl/gpio_logic_high.v"
`include "gl/mgmt_protect_hv.v"
`include "gl/gpio_control_block.v"
`include "gl/gpio_defaults_block.v"
`include "gl/gpio_logic_high.v"
`include "gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
`include "gl/caravan.v"
`else
`include "mgmt_soc.v"
`include "housekeeping_spi.v"
`include "caravel_clocking.v"
`include "mgmt_core.v"
`include "gl/caravan.v"
`else
`include "digital_pll.v"
`include "DFFRAM.v"
`include "DFFRAMBB.v"
`include "storage.v"
`include "caravel_clocking.v"
`include "user_id_programming.v"
`include "clock_div.v"
`include "storage_bridge_wb.v"
`include "mprj_io.v"
`include "chip_io_alt.v"
`include "housekeeping_spi.v"
`include "housekeeping.v"
`include "mprj_logic_high.v"
`include "mprj2_logic_high.v"
`include "mprj2_logic_high.v"
`include "mgmt_protect.v"
`include "mgmt_protect_hv.v"
`include "mgmt_protect_hv.v"
`include "gpio_control_block.v"
`include "gpio_defaults_block.v"
`include "gpio_logic_high.v"
`include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
`include "caravan.v"
`endif
`include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
`include "mgmt_core_wrapper.v"
`include "caravan.v"
`endif
`include "simple_por.v"
`include "sram_1rw1r_32_256_8_sky130.v"
`include "simple_por.v"
`endif

65
verilog/rtl/caravel_netlists.v
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@ -20,13 +20,13 @@
`ifdef SIM
`include "defines.v"
`include "user_defines.v"
`include "pads.v"
`include "defines.v"
`include "user_defines.v"
`include "pads.v"
/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
`ifdef EF_STYLE
`ifdef EF_STYLE
`include "libs.ref/verilog/sky130_fd_io/sky130_fd_io.v"
`include "libs.ref/verilog/sky130_fd_io/sky130_ef_io.v"
`include "libs.ref/verilog/sky130_fd_io/sky130_ef_io__gpiov2_pad_wrapped.v"
@ -35,7 +35,7 @@
`include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
`include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
`include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
`else
`else
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io__gpiov2_pad_wrapped.v"
@ -44,9 +44,9 @@
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
`endif
`endif
`ifdef GL
`ifdef GL
`include "gl/mgmt_core.v"
`include "gl/digital_pll.v"
`include "gl/DFFRAM.v"
@ -54,36 +54,35 @@
`include "gl/user_id_programming.v"
`include "gl/chip_io.v"
`include "gl/mprj_logic_high.v"
`include "gl/mprj2_logic_high.v"
`include "gl/mprj2_logic_high.v"
`include "gl/mgmt_protect.v"
`include "gl/mgmt_protect_hv.v"
`include "gl/mgmt_protect_hv.v"
`include "gl/gpio_control_block.v"
`include "gl/gpio_defaults_block.v"
`include "gl/gpio_logic_high.v"
`include "gl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
`include "gl/caravel.v"
`else
`include "gl/caravel.v"
`else
`include "digital_pll.v"
`include "caravel_clocking.v"
`include "user_id_programming.v"
`include "clock_div.v"
`include "mprj_io.v"
`include "chip_io.v"
`include "housekeeping_spi.v"
`include "housekeeping.v"
`include "mprj_logic_high.v"
`include "mprj2_logic_high.v"
`include "mgmt_protect.v"
`include "mgmt_protect_hv.v"
`include "gpio_control_block.v"
`include "gpio_defaults_block.v"
`include "gpio_logic_high.v"
`include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
`include "mgmt_core_wrapper.v"
`include "caravel.v"
`endif
`include "digital_pll.v"
`include "caravel_clocking.v"
`include "user_id_programming.v"
`include "clock_div.v"
`include "mprj_io.v"
`include "chip_io.v"
`include "housekeeping_spi.v"
`include "housekeeping.v"
`include "mprj_logic_high.v"
`include "mprj2_logic_high.v"
`include "mgmt_protect.v"
`include "mgmt_protect_hv.v"
`include "gpio_control_block.v"
`include "gpio_defaults_block.v"
`include "gpio_logic_high.v"
`include "sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v"
`include "mgmt_core_wrapper.v"
`include "caravel.v"
`endif
`include "simple_por.v"
`include "simple_por.v"
`endif