mirror of https://github.com/efabless/caravel.git
Added testbench for checking that the housekeeping SPI is accessible when
the user area is powered down. Because this requires some changes to the padframe definition, this testbench currently fails.
This commit is contained in:
Tim Edwards
parent
9fb3925649
commit
1d359690ac
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@ -0,0 +1,86 @@
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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PDK_PATH = $(PDK_ROOT)/sky130A
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VERILOG_PATH = ../../../..
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RTL_PATH = $(VERILOG_PATH)/rtl
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BEHAVIOURAL_MODELS = ../../
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# Temporary: Path to management SoC wrapper repository
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MGMT_WRAPPER_PATH = ~/gits/caravel_pico/verilog/rtl
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FIRMWARE_PATH = ../..
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GCC_PATH?=/ef/apps/bin
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GCC_PREFIX?=riscv32-unknown-elf
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SIM_DEFINES = -DFUNCTIONAL -DSIM
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SIM?=RTL
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.SUFFIXES:
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PATTERN = hkspi_power
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all: ${PATTERN:=.vcd}
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hex: ${PATTERN:=.hex}
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%.vvp: %_tb.v %.hex
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ifeq ($(SIM),RTL)
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iverilog -Ttyp $(SIM_DEFINES) -I $(BEHAVIOURAL_MODELS) \
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-I $(PDK_PATH) -I $(RTL_PATH) -I $(MGMT_WRAPPER_PATH) \
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$< -o $@
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else
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iverilog -Ttyp $(SIM_DEFINES) -DGL -I $(BEHAVIOURAL_MODELS) \
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-I $(PDK_PATH) -I $(VERILOG_PATH) -I $(RTL_PATH) \
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$< -o $@
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endif
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%.vcd: %.vvp
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vvp $<
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%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s check-env
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${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
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%.hex: %.elf
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${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
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# to fix flash base address
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sed -i 's/@10000000/@00000000/g' $@
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%.bin: %.elf
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${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
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check-env:
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ifndef PDK_ROOT
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$(error PDK_ROOT is undefined, please export it before running make)
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endif
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ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
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$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
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endif
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ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
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$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
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endif
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# check for efabless style installation
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ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
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SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
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endif
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# ---- Clean ----
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clean:
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rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
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.PHONY: clean hex all
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@ -0,0 +1,92 @@
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/*
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "../../defs.h"
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// --------------------------------------------------------
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void putchar(char c)
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{
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if (c == '\n')
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putchar('\r');
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reg_uart_data = c;
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}
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void print(const char *p)
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{
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while (*p)
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putchar(*(p++));
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}
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// --------------------------------------------------------
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void main()
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{
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// This program is just to keep the processor busy while the
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// housekeeping SPI is being accessed, to show that the
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// processor is interrupted only when the reset is applied
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// through the SPI.
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// Configure I/O: High 16 bits of user area used for a 16-bit
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// word to write and be detected by the testbench verilog.
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// Only serial Tx line is used in this testbench. It connects
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// to mprj_io[6]. Since all lines of the chip are input or
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// high impedence on startup, the I/O has to be configured
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// for output
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reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
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// Apply configuration
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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// Start test
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reg_mprj_datal = 0xa0000000;
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// Set clock to 64 kbaud and enable the UART
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reg_uart_clkdiv = 625;
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reg_uart_enable = 1;
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// Test message
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print("\n");
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print(" ____ _ ____ ____\n");
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print(" | _ \\(_) ___ ___/ ___| ___ / ___|\n");
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print(" | |_) | |/ __/ _ \\___ \\ / _ \\| |\n");
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print(" | __/| | (_| (_) |__) | (_) | |___\n");
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print(" |_| |_|\\___\\___/____/ \\___/ \\____|\n");
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reg_mprj_datal = 0xab000000;
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}
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@ -0,0 +1,430 @@
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*
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* StriVe housekeeping SPI testbench with the user project powered
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* down. The same as testbench "hkspi" but with user power set to
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* zero.
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*/
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`timescale 1 ns / 1 ps
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`include "__uprj_netlists.v"
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`include "caravel_netlists.v"
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`include "spiflash.v"
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`include "tbuart.v"
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module hkspi_power_tb;
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reg clock;
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reg SDI, CSB, SCK, RSTB;
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reg power1, power2;
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wire gpio;
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wire [15:0] checkbits;
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wire [37:0] mprj_io;
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wire uart_tx;
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wire uart_rx;
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wire flash_csb;
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wire flash_clk;
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wire flash_io0;
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wire flash_io1;
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wire flash_io2;
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wire flash_io3;
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wire SDO;
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always #10 clock <= (clock === 1'b0);
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initial begin
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clock = 0;
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power1 <= 1'b0;
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power2 <= 1'b0;
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#200;
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power1 <= 1'b1;
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#200;
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power2 <= 1'b1;
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end
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// The main testbench is here. Put the housekeeping SPI into
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// pass-thru mode and read several bytes from the flash SPI.
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// First define tasks for SPI functions
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task start_csb;
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begin
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SCK <= 1'b0;
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SDI <= 1'b0;
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CSB <= 1'b0;
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#50;
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end
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endtask
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task end_csb;
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begin
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SCK <= 1'b0;
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SDI <= 1'b0;
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CSB <= 1'b1;
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#50;
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end
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endtask
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task write_byte;
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input [7:0] odata;
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begin
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SCK <= 1'b0;
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for (i=7; i >= 0; i--) begin
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#50;
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SDI <= odata[i];
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#50;
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SCK <= 1'b1;
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#100;
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SCK <= 1'b0;
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end
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end
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endtask
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task read_byte;
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output [7:0] idata;
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begin
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SCK <= 1'b0;
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SDI <= 1'b0;
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for (i=7; i >= 0; i--) begin
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#50;
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idata[i] = SDO;
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#50;
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SCK <= 1'b1;
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#100;
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SCK <= 1'b0;
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end
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end
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endtask
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task read_write_byte
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(input [7:0] odata,
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output [7:0] idata);
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begin
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SCK <= 1'b0;
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for (i=7; i >= 0; i--) begin
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#50;
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SDI <= odata[i];
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idata[i] = SDO;
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#50;
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SCK <= 1'b1;
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#100;
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SCK <= 1'b0;
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end
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end
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endtask
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integer i;
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// Now drive the digital signals on the housekeeping SPI
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reg [7:0] tbdata;
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initial begin
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$dumpfile("hkspi_power.vcd");
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$dumpvars(0, hkspi_power_tb);
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CSB <= 1'b1;
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SCK <= 1'b0;
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SDI <= 1'b0;
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RSTB <= 1'b0;
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// Delay, then bring chip out of reset
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#1000;
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RSTB <= 1'b1;
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#2000;
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// First do a normal read from the housekeeping SPI to
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// make sure the housekeeping SPI works.
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start_csb();
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write_byte(8'h40); // Read stream command
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write_byte(8'h03); // Address (register 3 = product ID)
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read_byte(tbdata);
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end_csb();
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#10;
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$display("Read data = 0x%02x (should be 0x11)", tbdata);
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// Toggle external reset
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start_csb();
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write_byte(8'h80); // Write stream command
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write_byte(8'h0b); // Address (register 7 = external reset)
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write_byte(8'h01); // Data = 0x01 (apply external reset)
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end_csb();
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start_csb();
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write_byte(8'h80); // Write stream command
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write_byte(8'h0b); // Address (register 7 = external reset)
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write_byte(8'h00); // Data = 0x00 (release external reset)
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end_csb();
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// Read all registers (0 to 18)
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start_csb();
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write_byte(8'h40); // Read stream command
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write_byte(8'h00); // Address (register 3 = product ID)
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read_byte(tbdata);
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$display("Read register 0 = 0x%02x (should be 0x00)", tbdata);
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if(tbdata !== 8'h00) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed"); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 1 = 0x%02x (should be 0x04)", tbdata);
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if(tbdata !== 8'h04) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed"); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 2 = 0x%02x (should be 0x56)", tbdata);
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if(tbdata !== 8'h56) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 3 = 0x%02x (should be 0x11)", tbdata);
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if(tbdata !== 8'h11) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed, %02x", tbdata); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed, %02x", tbdata); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 4 = 0x%02x (should be 0x00)", tbdata);
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if(tbdata !== 8'h00) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed"); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 5 = 0x%02x (should be 0x00)", tbdata);
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if(tbdata !== 8'h00) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed"); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 6 = 0x%02x (should be 0x00)", tbdata);
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if(tbdata !== 8'h00) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed"); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 7 = 0x%02x (should be 0x00)", tbdata);
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if(tbdata !== 8'h00) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed"); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 8 = 0x%02x (should be 0x02)", tbdata);
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if(tbdata !== 8'h02) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed"); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 9 = 0x%02x (should be 0x01)", tbdata);
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if(tbdata !== 8'h01) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed"); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 10 = 0x%02x (should be 0x00)", tbdata);
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if(tbdata !== 8'h00) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed"); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 11 = 0x%02x (should be 0x00)", tbdata);
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if(tbdata !== 8'h00) begin
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`ifdef GL
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$display("Monitor: Test HK SPI (GL) Failed"); $finish;
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`else
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$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
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`endif
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end
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read_byte(tbdata);
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$display("Read register 12 = 0x%02x (should be 0x00)", tbdata);
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if(tbdata !== 8'h00) begin
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`ifdef GL
|
||||
$display("Monitor: Test HK SPI (GL) Failed"); $finish;
|
||||
`else
|
||||
$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
|
||||
`endif
|
||||
end
|
||||
read_byte(tbdata);
|
||||
$display("Read register 13 = 0x%02x (should be 0xff)", tbdata);
|
||||
if(tbdata !== 8'hff) begin
|
||||
`ifdef GL
|
||||
$display("Monitor: Test HK SPI (GL) Failed"); $finish;
|
||||
`else
|
||||
$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
|
||||
`endif
|
||||
end
|
||||
read_byte(tbdata);
|
||||
$display("Read register 14 = 0x%02x (should be 0xef)", tbdata);
|
||||
if(tbdata !== 8'hef) begin
|
||||
`ifdef GL
|
||||
$display("Monitor: Test HK SPI (GL) Failed"); $finish;
|
||||
`else
|
||||
$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
|
||||
`endif
|
||||
end
|
||||
read_byte(tbdata);
|
||||
$display("Read register 15 = 0x%02x (should be 0xff)", tbdata);
|
||||
if(tbdata !== 8'hff) begin
|
||||
`ifdef GL
|
||||
$display("Monitor: Test HK SPI (GL) Failed"); $finish;
|
||||
`else
|
||||
$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
|
||||
`endif
|
||||
end
|
||||
read_byte(tbdata);
|
||||
$display("Read register 16 = 0x%02x (should be 0x03)", tbdata);
|
||||
if(tbdata !== 8'h03) begin
|
||||
`ifdef GL
|
||||
$display("Monitor: Test HK SPI (GL) Failed"); $finish;
|
||||
`else
|
||||
$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
|
||||
`endif
|
||||
end
|
||||
read_byte(tbdata);
|
||||
$display("Read register 17 = 0x%02x (should be 0x12)", tbdata);
|
||||
if(tbdata !== 8'h12) begin
|
||||
`ifdef GL
|
||||
$display("Monitor: Test HK SPI (GL) Failed"); $finish;
|
||||
`else
|
||||
$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
|
||||
`endif
|
||||
end
|
||||
read_byte(tbdata);
|
||||
$display("Read register 18 = 0x%02x (should be 0x04)", tbdata);
|
||||
if(tbdata !== 8'h04) begin
|
||||
`ifdef GL
|
||||
$display("Monitor: Test HK SPI (GL) Failed"); $finish;
|
||||
`else
|
||||
$display("Monitor: Test HK SPI (RTL) Failed"); $finish;
|
||||
`endif
|
||||
end
|
||||
|
||||
end_csb();
|
||||
|
||||
`ifdef GL
|
||||
$display("Monitor: Test HK SPI (GL) Passed");
|
||||
`else
|
||||
$display("Monitor: Test HK SPI (RTL) Passed");
|
||||
`endif
|
||||
|
||||
#10000;
|
||||
$finish;
|
||||
end
|
||||
|
||||
wire VDD3V3;
|
||||
wire VDD1V8;
|
||||
wire VSS;
|
||||
|
||||
assign VDD3V3 = power1;
|
||||
assign VDD1V8 = power2;
|
||||
assign VSS = 1'b0;
|
||||
|
||||
wire hk_sck;
|
||||
wire hk_csb;
|
||||
wire hk_sdi;
|
||||
|
||||
assign hk_sck = SCK;
|
||||
assign hk_csb = CSB;
|
||||
assign hk_sdi = SDI;
|
||||
|
||||
assign checkbits = mprj_io[31:16];
|
||||
assign uart_tx = mprj_io[6];
|
||||
assign mprj_io[5] = uart_rx;
|
||||
assign mprj_io[4] = hk_sck;
|
||||
assign mprj_io[3] = hk_csb;
|
||||
assign mprj_io[2] = hk_sdi;
|
||||
assign SDO = mprj_io[1];
|
||||
|
||||
caravel uut (
|
||||
.vddio (VDD3V3),
|
||||
.vssio (VSS),
|
||||
.vdda (VDD3V3),
|
||||
.vssa (VSS),
|
||||
.vccd (VDD1V8),
|
||||
.vssd (VSS),
|
||||
.vdda1 (VSS), // User power supplies grounded
|
||||
.vdda2 (VSS), // for this testbench.
|
||||
.vssa1 (VSS),
|
||||
.vssa2 (VSS),
|
||||
.vccd1 (VSS),
|
||||
.vccd2 (VSS),
|
||||
.vssd1 (VSS),
|
||||
.vssd2 (VSS),
|
||||
.clock (clock),
|
||||
.gpio (gpio),
|
||||
.mprj_io (mprj_io),
|
||||
.flash_csb(flash_csb),
|
||||
.flash_clk(flash_clk),
|
||||
.flash_io0(flash_io0),
|
||||
.flash_io1(flash_io1),
|
||||
.resetb (RSTB)
|
||||
);
|
||||
|
||||
spiflash #(
|
||||
.FILENAME("hkspi_power.hex")
|
||||
) spiflash (
|
||||
.csb(flash_csb),
|
||||
.clk(flash_clk),
|
||||
.io0(flash_io0),
|
||||
.io1(flash_io1),
|
||||
.io2(), // not used
|
||||
.io3() // not used
|
||||
);
|
||||
|
||||
tbuart tbuart (
|
||||
.ser_rx(uart_tx)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`default_nettype wire
|
||||
|
|
@ -35,6 +35,7 @@
|
|||
`include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
|
||||
`include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
|
||||
`include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
|
||||
`include "libs.ref/verilog/sky130_sram_macros/sky130_sram_1kbyte_1rw1r_32x256_8.v"
|
||||
`else
|
||||
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
|
||||
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
|
||||
|
|
@ -45,6 +46,7 @@
|
|||
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
|
||||
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
|
||||
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
|
||||
`include "libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
|
||||
`endif
|
||||
|
||||
`ifdef GL
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@
|
|||
`include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
|
||||
`include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
|
||||
`include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
|
||||
`include "libs.ref/verilog/sky130_sram_macros/sky130_sram_1kbyte_1rw1r_32x256_8.v"
|
||||
`else
|
||||
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
|
||||
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
|
||||
|
|
@ -44,6 +45,7 @@
|
|||
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
|
||||
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
|
||||
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
|
||||
`include "libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
|
||||
`endif
|
||||
|
||||
`ifdef GL
|
||||
|
|
|
|||
Loading…
Reference in New Issue