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caravel
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Made the same corrections to caravan as were made to caravel 

(clock -> clock_core in caravel_clocking, VPWR -> vccd_core and
VGND -> vssd_core in the instances of modules that were pulled from
the management SoC to the top level).
This commit is contained in:
Tim Edwards 2021-11-17 09:06:42 -05:00
parent b5fe87304a
commit 5f1a0029f5
1 changed files with 7 additions and 7 deletions
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14
verilog/rtl/caravan.v
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@ -665,11 +665,11 @@ module caravan (
caravel_clocking clocking(
`ifdef USE_POWER_PINS
.vdd1v8(VPWR),
.vss(VGND),
.vdd1v8(vccd_core),
.vss(vssd_core),
`endif
.ext_clk_sel(ext_clk_sel),
.ext_clk(clock),
.ext_clk(clock_core),
.pll_clk(pll_clk),
.pll_clk90(pll_clk90),
.resetb(resetb),
@ -685,8 +685,8 @@ module caravan (
digital_pll pll (
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.resetb(resetb),
.enable(spi_pll_ena),
@ -701,8 +701,8 @@ module caravan (
housekeeping housekeeping (
`ifdef USE_POWER_PINS
.vdd(VPWR),
.vss(VGND),
.vdd(vccd_core),
.vss(vssd_core),
`endif
.wb_clk_i(caravel_clk),