From 5f1a0029f519aab6400e53d345f0321e3e012adc Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Wed, 17 Nov 2021 09:06:42 -0500
Subject: [PATCH] Made the same corrections to caravan as were made to caravel
 (clock -> clock_core in caravel_clocking, VPWR -> vccd_core and VGND ->
 vssd_core in the instances of modules that were pulled from the management
 SoC to the top level).

---
 verilog/rtl/caravan.v | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v
index 16579bf9..10ea877e 100644
--- a/verilog/rtl/caravan.v
+++ b/verilog/rtl/caravan.v
@@ -665,11 +665,11 @@ module caravan (
 
     caravel_clocking clocking(
 	`ifdef USE_POWER_PINS
-	    .vdd1v8(VPWR),
-	    .vss(VGND),
+	    .vdd1v8(vccd_core),
+	    .vss(vssd_core),
 	`endif
 	.ext_clk_sel(ext_clk_sel),
-	.ext_clk(clock),
+	.ext_clk(clock_core),
 	.pll_clk(pll_clk),
 	.pll_clk90(pll_clk90),
 	.resetb(resetb),
@@ -685,8 +685,8 @@ module caravan (
 
     digital_pll pll (
 	`ifdef USE_POWER_PINS
-	    .VPWR(VPWR),
-	    .VGND(VGND),
+	    .VPWR(vccd_core),
+	    .VGND(vssd_core),
 	`endif
 	.resetb(resetb),
 	.enable(spi_pll_ena),
@@ -701,8 +701,8 @@ module caravan (
 
     housekeeping housekeeping (
 	`ifdef USE_POWER_PINS
-	    .vdd(VPWR),
-	    .vss(VGND),
+	    .vdd(vccd_core),
+	    .vss(vssd_core),
 	`endif
 
 	.wb_clk_i(caravel_clk),