mirror of https://github.com/efabless/caravel.git
Added a script which parses the file "user_defines.v" in
verilog/rtl/, and creates all the layout files needed to represent all unique combinations of defaults used in the file. Not done: Modifying the top level layout to use the correct defaults (because the top level layout does not yet exist).
This commit is contained in:
Tim Edwards
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#!/usr/bin/env python3
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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#----------------------------------------------------------------------
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#
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# gen_gpio_defaults.py ---
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#
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# Manipulate the magic database and GDS to create and apply defaults
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# to the GPIO control blocks based on the user's specification in the
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# user_defines.v file.
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#
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# The GPIO defaults block contains 13 bits that set the state of the
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# GPIO on power-up. GPIOs 0 to 4 in the user project area are fixed
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# and cannot be modified (to maintain access to the housekeeping SPI
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# on startup). GPIOs 5 to 37 are by default set to be an input pad
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# controlled by the user project. The file "user_defines.v" contains
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# the state specified by the user for each GPIO pad, and is what is
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# used in verilog simulation.
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#
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# This script parses the user_defines.v file to determine the state
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# of each GPIO. Then it creates as many new layouts as needed to
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# represent all unique states, modifies the caravel.mag layout
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# to replace the default layouts with the new ones as needed, and
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# generates GDS files for each of the layouts.
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#
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# gpio_defaults_block layout map:
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# Positions marked (in microns) for value = 0. For value = 1, move
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# the via 0.69um to the left. The given position is the lower left
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# corner position of the via. The via itself is 0.17um x 0.17um.
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# The values below are for the file gpio_defaults_block_1403.
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# Positions marked "Y" for "Programmed One?" are already moved to
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# the left, and so should be move 0.69um to the right if the bit
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# should be zero.
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#
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# Signal Via position (um)
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# name X Y
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#-------------------------------------------------------------------
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# gpio_defaults[0] 5.435 4.165
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# gpio_defaults[1] 6.815 3.825
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# gpio_defaults[2] 8.195 4.165
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# gpio_defaults[3] 9.575 3.825
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# gpio_defaults[4] 10.955 3.825
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# gpio_defaults[5] 12.565 3.825
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# gpio_defaults[6] 14.865 3.825
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# gpio_defaults[7] 17.165 3.825
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# gpio_defaults[8] 19.465 3.825
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# gpio_defaults[9] 21.765 3.825
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# gpio_defaults[10] 24.755 3.825
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# gpio_defaults[11] 27.055 3.825
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# gpio_defaults[12] 23.605 4.165
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#-------------------------------------------------------------------
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import os
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import sys
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import re
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def usage():
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print('Usage:')
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print('gen_gpio_defaults.py [<path_to_project>]')
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print('')
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print('where:')
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print(' <path_to_project> is the path to the project top level directory.')
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print('')
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print(' If <path_to_project> is not given, then it is assumed to be the cwd.')
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print(' The file "user_defines.v" must exist in verilog/rtl/ relative to')
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print(' <path_to_project>.')
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return 0
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if __name__ == '__main__':
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# Coordinate pairs in microns for the zero position on each bit
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via_pos = [[5.435, 4.165], [6.815, 3.825], [8.195, 4.165], [9.575, 3.825],
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[10.955, 3.825], [12.565, 3.825], [14.865, 3.825], [17.165, 3.825],
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[19.465, 3.825], [21.765, 3.825], [24.755, 3.825], [27.055, 3.825],
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[23.605, 4.165]]
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optionlist = []
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arguments = []
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debugmode = False
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reportmode = False
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for option in sys.argv[1:]:
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if option.find('-', 0) == 0:
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optionlist.append(option)
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else:
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arguments.append(option)
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if len(arguments) > 2:
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print("Wrong number of arguments given to gen_gpio_defaults.py.")
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usage()
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sys.exit(0)
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if '-debug' in optionlist:
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debugmode = True
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if '-report' in optionlist:
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reportmode = True
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user_project_path = None
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if len(arguments) == 0:
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user_project_path = os.getcwd()
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else:
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user_project_path = arguments[0]
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if not os.path.isdir(user_project_path):
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print('Error: Project path "' + user_project_path + '" does not exist or is not readable.')
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sys.exit(1)
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magpath = user_project_path + '/mag'
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gdspath = user_project_path + '/gds'
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vpath = user_project_path + '/verilog'
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# Check paths
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if not os.path.isdir(gdspath):
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print('No directory ' + gdspath + ' found (path to GDS).')
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sys.exit(1)
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if not os.path.isdir(vpath):
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print('No directory ' + vpath + ' found (path to verilog).')
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sys.exit(1)
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if not os.path.isdir(magpath):
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print('No directory ' + magpath + ' found (path to magic databases).')
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sys.exit(1)
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# Parse the user defines verilog file
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kvpairs = {}
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if os.path.isfile(vpath + '/rtl/user_defines.v'):
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with open(vpath + '/rtl/user_defines.v', 'r') as ifile:
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infolines = ifile.read().splitlines()
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for line in infolines:
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tokens = line.split()
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if len(tokens) >= 3:
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if tokens[0] == '`define':
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if tokens[2][0] == '`':
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# If definition is nested, substitute value.
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tokens[2] = kvpairs[tokens[2]]
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kvpairs['`' + tokens[1]] = tokens[2]
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else:
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print('Error: No user_defines.v file found.')
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sys.exit(1)
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# Generate zero and one coordinates for each via
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llx_zero = []
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lly_zero = []
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urx_zero = []
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ury_zero = []
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llx_one = []
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lly_one = []
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urx_one = []
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ury_one = []
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zero_string = []
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one_string = []
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for i in range(0, 13):
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llx_zero = int(via_pos[i][0] * 200)
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lly_zero = int(via_pos[i][1] * 200)
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urx_zero = llx_zero + 34
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ury_zero = lly_zero + 34
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llx_one = llx_zero - 138
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lly_one = lly_zero
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urx_one = urx_zero - 138
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ury_one = ury_zero
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zero_string.append('rect {:d} {:d} {:d} {:d}'.format(llx_zero, lly_zero, urx_zero, ury_zero))
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one_string.append('rect {:d} {:d} {:d} {:d}'.format(llx_one, lly_one, urx_one, ury_one))
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# Create new cells for each unique type
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print('Step 1: Create new cells for new GPIO default vectors.')
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for i in range(5, 38):
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config_name = '`USER_CONFIG_GPIO_' + str(i) + '_INIT'
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try:
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config_value = kvpairs[config_name]
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except:
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print('No configuration specified for GPIO ' + str(i) + '; skipping.')
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continue
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try:
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default_str = config_value[-4:]
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binval = '{:013b}'.format(int(default_str, 16))
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except:
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print('Error: Default value ' + config_value + ' is not a 4-digit hex number; skipping')
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continue
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cell_name = 'gpio_defaults_block_' + default_str
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mag_file = magpath + '/' + cell_name + '.mag'
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if not os.path.isfile(mag_file):
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# A cell with this set of defaults doesn't exist, so make it
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# First read the 0000 cell, then write to mag_path while
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# changing the position of vias on the "1" bits
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# Record which bits need to be set
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bitflips = []
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for j in range(0, 13):
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if binval[12 - j] == '1':
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bitflips.append(j)
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with open(magpath + '/gpio_defaults_block_0000.mag', 'r') as ifile:
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maglines = ifile.read().splitlines()
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outlines = []
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for magline in maglines:
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is_flipped = False
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for bitflip in bitflips:
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if magline == zero_string[bitflip]:
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is_flipped = True
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break
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if is_flipped:
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outlines.append(one_string[bitflip])
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else:
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outlines.append(magline)
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print('Creating new layout file ' + mag_file)
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with open(mag_file, 'w') as ofile:
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for outline in outlines:
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print(outline, file=ofile)
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else:
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print('Layout file ' + mag_file + ' already exists and does not need to be generated.')
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print('Step 2: Modify top-level layouts to use the specified defaults.')
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# WIP
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print('Done.')
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sys.exit(0)
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