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Corrected an error in the bitbang testbench (but it does not cause the 

testbench to pass).
This commit is contained in:
Tim Edwards 2021-10-19 23:10:51 -04:00
parent 184f4a637c
commit 000a5266ef
1 changed files with 6 additions and 6 deletions
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12
verilog/dv/caravel/mgmt_soc/mprj_bitbang/mprj_bitbang_tb.v
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@ -136,13 +136,13 @@ module mprj_bitbang_tb;
start_csb();
write_byte(8'h80);
write_byte(8'h13);
write_byte(8'h07);
write_byte(8'h07 << 1);
end_csb();
start_csb();
write_byte(8'h80);
write_byte(8'h13);
write_byte(8'h03);
write_byte(8'h03 << 1);
end_csb();
end
endtask
@ -152,25 +152,25 @@ module mprj_bitbang_tb;
start_csb();
write_byte(8'h80);
write_byte(8'h13);
write_byte(8'h07);
write_byte(8'h07 << 1);
end_csb();
start_csb();
write_byte(8'h80);
write_byte(8'h13);
write_byte(8'h05);
write_byte(8'h05 << 1);
end_csb();
start_csb();
write_byte(8'h80);
write_byte(8'h13);
write_byte(8'h07);
write_byte(8'h07 << 1);
end_csb();
start_csb();
write_byte(8'h80);
write_byte(8'h13);
write_byte(8'h03);
write_byte(8'h03 << 1);
end_csb();
end
endtask