mirror of https://github.com/efabless/caravel.git
Updated pinout in documentation (doc/README file)
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Tim Edwards
parent
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doc/README
282
doc/README
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@ -1,11 +1,8 @@
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Definitions:
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caravel_openframe: Version with one wrapper for user
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project only.
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caravel_openframe: Version with two wrappers for user
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project area and management core
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caravel_harness: Version with wrappers for user project
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area and management core.
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caravel_pico: PicoRV32, as a drop-in module for caravel_harness
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caravel_pico: PicoRV32, as a drop-in module for caravel_openframe.
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Harness definition:
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Management SoC and User Project are both wrappers for drop-in
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@ -22,8 +19,24 @@ Harness definition:
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each GPIO. Can be configured with a text file. SPI pins are
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fixed for operation on startup.
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On power-up, the SPI automatically configures the GPIO. Manual
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load is possible from both the SPI and from the wishbone bus.
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(To be done) On power-up, the SPI automatically configures the
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GPIO. Manual load is possible from both the SPI and from the
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wishbone bus.
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All functions within the harness but outside the management SoC
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are incorporated into one large module called "housekeeping".
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This includes a number of registers for all the included
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functions, with a "front door" SPI interface connected to the
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padframe through GPIO pins 1 to 4, and a "back door" wishbone
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interface connected to the management SoC. The management Soc
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needs to reserve the memory block at 0x26000000 for the
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housekeeping module. The housekeeping module exchanges data
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with the management SoC via an interface that uses the byte-
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wide SPI register data. A small state machine reads four
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contiguous wishbone addresses and an address decoder determines
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the corresponding SPI register. The state machine stalls the
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SoC until all four bytes have been handled before returning the
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acknowledge signal.
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Openframe definition:
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There is only one area which is the User Project, with a wrapper
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@ -33,21 +46,25 @@ Openframe definition:
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SPI, POR, and GPIO control. Operation is essentially the same as
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the above (harness definition).
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There is currently no specific module for the open frame by itself.
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This needs to be defined, with the management SoC wrapper removed
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and the wrapper pins reworked.
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MPW-one compatibility:
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Looks like the harness, but the logic analyzer and management-
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protect is part of the harness and the user area wrapper matches
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that for MPW-one.
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The same as the harness definition but with a wrapper pin arrangement
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corresponding to MPW-one.
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MPW-two compatibility:
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Looks like the harness, but the logic analyzer and management-
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protect is part of the harness and the user area wrapper matches
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that for MPW-two.
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The same as the harness definition but with a wrapper pin arrangement
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corresponding to MPW-two.
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Caravel-pico definition:
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Caravel-pico is a version of the PicoRV32 Management SoC from
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MPW-two, but without the GPIO control, clocking control, DLL,
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housekeeping SPI, and logic analyzer. It mainly just exports
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the Wishbone bus interface to the user project area.
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and housekeeping SPI. It mainly just exports the Wishbone bus
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interface to the user project area and housekeeping, with
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housekeeping defined in memory block 0x26000000 and the user
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project area defined in memory block 0x30000000 (as before).
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Pinouts for Caravel (any version)
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----------------------------------------------
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@ -57,7 +74,6 @@ Pinouts for Caravel (any version)
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vccd1, vccd2, vssd1, vssd2
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Management SoC signals:
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debug (or JTAG, management)
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gpio
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clock
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resetb
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@ -76,28 +92,30 @@ User project area pinout (openframe)
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vdda1, vdda2, vssa1, vssa2,
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vccd1, vccd2, vssd1, vssd2
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Wishbone bus (exported to SPI):
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Wishbone bus (exported to housekeeping):
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wb_clk_i
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wb_rst_i
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wbs_stb_i
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wbs_cyc_i
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wbs_we_i
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wbs_sel_i[3:0]
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wbs_dat_i[31:0]
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wbs_adr_i[31:0]
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wbs_ack_o
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wbs_dat_o[31:0]
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wbs_ack_o
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wbs_stb_i
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wbs_dat_i[31:0]
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GPIO:
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GPIO (3-pin interfaces; all else handled through housekeeping):
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io_in[37:0]
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io_out[37:0]
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io_oeb[37:0]
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GPIO (single):
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GPIO (single pin not related to the other GPIO):
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gpio_out
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gpio_in
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gpio_oeb
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gpio_ieb
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gpio_mode0
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gpio_mode1
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Flash controller:
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flash_clk
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@ -121,13 +139,34 @@ User project area pinout (openframe)
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flash_io2_ieb
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flash_io3_ieb
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Essentials:
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Essentials (from power-on-reset and clocking):
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resetb
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core_clk
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Miscellaneous:
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IRQ (input from housekeeping from SPI and routed pins):
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irq_spi[2:0]
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Miscellaneous (independent clock source from clocking control):
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user_clock2
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user_irq[2:0]
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Module status (optional modules with I/O handled through housekeeping)
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(if not implemented, then these should be tied low)
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qspi_enabled
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uart_enabled
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spi_enabled
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debug_mode
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Module interfaces (optional modules wth I/O handled though housekeeping)
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(if not implemented, then inputs should be tied low/high as appropriate)
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ser_tx (UART transmit)
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ser_rx (UART receive)
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spi_sdi (SPI master data in)
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spi_sdo (SPI master data out)
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spi_sck (SPI master clock out)
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spi_csb (SPI master select out)
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debug_in (debug pin on gpio 0)
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debug_out (debug pin on gpio 0)
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debug_oeb (debug pin on gpio 0)
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User project area pinout (harness)
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@ -152,18 +191,29 @@ User project area pinout (harness)
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io_in[37:0]
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io_out[37:0]
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io_oeb[37:0]
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analog_io[28:0]
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Miscellaneous:
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user_clock2
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user_irq[2:0]
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Management SoC pinout
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Management SoC pinout (mgmt_core_wrapper)
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----------------------------------------------
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Power supply:
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vccd_core
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vssd_core
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Essentials:
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core_rstn
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core_clk
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GPIO:
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gpio_out
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gpio_in
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gpio_oeb
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gpio_ieb
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gpio_out_pad
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gpio_in_pad
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gpio_mode0_pad
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gpio_mode1_pad
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gpio_outenb_pad
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gpio_inenb_pad
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Flash controller:
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flash_clk
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@ -181,140 +231,60 @@ Management SoC pinout
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flash_io2_oeb
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flash_io3_oeb
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Essentials:
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resetb
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core_clk
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Wishbone bus:
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mprj_ack_i
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mprj_dat_i[31:0]
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mprj_dat_o[31:0]
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(All peripherals)
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mprj_cyc_o
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mprj_stb_o
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mprj_we_o
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mprj_sel_o[3:0]
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mprj_adr_o[31:0]
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Interface pinout (standard = pass-through)
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----------------------------------------------
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Clocking (DLL)
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clock
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porb
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resetb
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core_clk
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Housekeeping SPI
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SCK
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CSB
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SDI
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SDO
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sdo_enb
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Flash pass-through:
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flash_clk_oeb
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flash_csb_oeb
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flash_io0_ieb
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flash_io1_ieb
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flash_io2_ieb
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flash_io3_ieb
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(plus management flash signals in from SoC/out to pads)
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Wishbone bus:
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mprj_ack_i
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mprj_dat_i[31:0]
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mprj_dat_o[31:0]
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mprj_cyc_o
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mprj_stb_o
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mprj_we_o
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mprj_sel_o[3:0]
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mprj_adr_o[31:0]
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User ID programming
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mask_rev[31:0]
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Interface pinout (MPW-one compatibility level)
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----------------------------------------------
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Clocking (DLL)
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clock
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porb
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resetb
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core_clk
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GPIO controller
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serial_data
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serial_clock
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serial_reset
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Housekeeping SPI
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SCK
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CSB
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SDI
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SDO
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sdo_enb
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Flash pass-through:
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flash_clk_oeb
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flash_csb_oeb
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flash_io0_ieb
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flash_io1_ieb
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flash_io2_ieb
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flash_io3_ieb
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(plus management flash signals in from SoC/out to pads)
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Wishbone bus:
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(User project)
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mprj_ack_i
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mprj_dat_i[31:0]
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mprj_dat_o[31:0]
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mprj_cyc_o
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mprj_stb_o
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mprj_we_o
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mprj_sel_o[3:0]
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mprj_adr_o[31:0]
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User ID programming
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mask_rev[31:0]
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Logic Analyzer
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la_io[127:0]
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la_oenb[127:0]
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Interface pinout (MPW-two compatibility level)
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----------------------------------------------
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Clocking (DLL)
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clock
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porb
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resetb
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core_clk
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GPIO controller
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serial_data
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serial_clock
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serial_reset
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Housekeeping SPI
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SCK
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CSB
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SDI
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SDO
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sdo_enb
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Wishbone bus:
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mprj_ack_i
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mprj_dat_i[31:0]
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mprj_dat_o[31:0]
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mprj_cyc_o
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mprj_stb_o
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mprj_we_o
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mprj_sel_o[3:0]
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mprj_adr_o[31:0]
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User ID programming
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mask_rev[31:0]
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(Housekeeping)
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hk_ack_i
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hk_stb_o
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hk_dat_i[31:0]
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Logic Analyzer
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la_input[127:0]
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la_output[127:0]
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la_oenb[127:0]
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la_iena[127:0]
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IRQ
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irq[5:0]
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Module status
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qspi_enabled
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uart_enabled
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spi_enabled
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debug_mode
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Module interfaces
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(UART)
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ser_tx
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ser_rx
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(SPI master)
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spi_sdi
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spi_csb
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spi_sck
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spi_sdo
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(Debug)
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debug_in
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debug_out
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debug_oeb
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(Logic Analyzer)
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la_input
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la_output
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la_oenb
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la_iena
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(SRAM read-only port)
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hkspi_sram_clk
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hkspi_sram_csb
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hkspi_sram_addr
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hkspi_sram_rdata
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CPU status
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trap
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