tangxifan
|
0bee70bee6
|
finish memory bank configuration protocol support.
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
e14c39e14c
|
update Verilog full testbench generation to support memory bank configuration protocol
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
ad7422359d
|
deploy compact constant values in Verilog codes
|
2020-06-11 19:31:13 -06:00 |
|
tangxifan
|
8ec8ac4118
|
bug fixed in flatten memory organization. Passed verification
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
b9aac3cbdf
|
updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
9e176b8d38
|
add fast configuration stats to log
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
8b3e79766c
|
add fast configuration option to fpga_verilog to speed up full testbench simulation
|
2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
b5e5182f52
|
frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
31c9a011dd
|
keep bug fixing for arch decoders
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
bdc9efb38f
|
bug fix in top-level testbench for frame-based decoders
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
986956e474
|
bug fix for arch decoder Verilog codes. Now Modelsim compiles ok.
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
6a72c66eb8
|
bug fixed for frame-based configuration memory in top-level full testbench
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
8aa665b3b2
|
bug fix in the Verilog codes for frame decoders
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
ece651ade2
|
bug fixed in the configuration chian errrors
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
cff5b5cfc1
|
break the configuration testbench. This commit is to spot which modification leads to the problem
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
4a0e1cd908
|
add fabric bitstream data structure and deploy it to Verilog testbench generation
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
5c5a044c68
|
add architecture decoder (for frame-based config memory) to Verilog writer
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
bba476fef4
|
add explicit port mapping support to Verilog testbench generator
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
8d2360a710
|
simplify include_netlist.v
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
1e2226e1c3
|
now use explicit port mapping in the verilog testbenches for reference benchmarks
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
69306faf22
|
add a new include netlist for all the fabric-related netlists
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
8f5a684b10
|
removed redundant include files in all the verilog netlists except the top one
|
2020-06-11 19:28:13 -06:00 |
|
tangxifan
|
185e574738
|
removed redundant include files in all the verilog netlists except the top one
|
2020-04-24 20:21:32 -06:00 |
|
tangxifan
|
e811f8bb21
|
plug in netlist manager and now the include_netlist appears in one unique file
|
2020-04-23 20:42:11 -06:00 |
|
tangxifan
|
a7d900088b
|
now generating simulation ini file will try to create directory first
|
2020-04-15 20:53:37 -06:00 |
|
tangxifan
|
2ffd174e6a
|
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
|
2020-04-15 15:48:33 -06:00 |
|
tangxifan
|
1fb37f4c71
|
improve directory creator to support same functionality as 'mkdir -p'
|
2020-04-08 12:55:09 -06:00 |
|
tangxifan
|
3369d724e9
|
bug fixing in Verilog top-level testbench generation
|
2020-04-05 17:50:11 -06:00 |
|
tangxifan
|
decc1dc4b2
|
debugged global gp input/output port support
|
2020-04-05 17:39:30 -06:00 |
|
tangxifan
|
5f4e7dc5d4
|
support gpinput and gpoutput ports in module manager and circuit library
|
2020-04-05 16:52:21 -06:00 |
|
tangxifan
|
bc47b3ca94
|
update verilog module writer to the global spy ports
|
2020-04-05 16:04:13 -06:00 |
|
tangxifan
|
836f722f20
|
start supporting global output ports in module manager
|
2020-04-05 15:19:46 -06:00 |
|
tangxifan
|
ff9cc50527
|
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
|
2020-03-27 20:09:50 -06:00 |
|
tangxifan
|
4bf0a63ae6
|
bug fixed for multiple io types defined in FPGA architectures
|
2020-03-27 16:32:15 -06:00 |
|
tangxifan
|
0c7aa2581d
|
update vpr8 version with hotfix on undriven pins in GSB
|
2020-03-08 14:58:56 -06:00 |
|
tangxifan
|
7fcd27e000
|
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
|
tangxifan
|
80bb2baae5
|
start verification and bug fixing
|
2020-02-28 14:29:01 -07:00 |
|
tangxifan
|
65c81e14b2
|
add simulation ini file writer
|
2020-02-27 18:01:47 -07:00 |
|
tangxifan
|
ae899f3b11
|
bug fixed for clock names
|
2020-02-27 16:51:55 -07:00 |
|
tangxifan
|
9b769cd8e4
|
bug fix for using renamed i/o names
|
2020-02-27 16:37:20 -07:00 |
|
tangxifan
|
b010fc1983
|
add warning to force formal_verification_top_netlist enabled
|
2020-02-27 13:28:21 -07:00 |
|
tangxifan
|
078f72320f
|
debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
|
2020-02-27 13:24:26 -07:00 |
|
tangxifan
|
f558405887
|
ported verilog testbench generator online. Split from fabric generator. Testing to be done
|
2020-02-27 12:33:09 -07:00 |
|
tangxifan
|
77529f4957
|
adapt top Verilog testbench generation
|
2020-02-26 21:30:21 -07:00 |
|
tangxifan
|
bb671acac3
|
add formal random Verilog testbench generation
|
2020-02-26 20:58:16 -07:00 |
|
tangxifan
|
e9adb4fdbc
|
add preconfig top module Verilog generation
|
2020-02-26 20:38:01 -07:00 |
|
tangxifan
|
25e0583636
|
add io location map data structure and start porting verilog testbench generator
|
2020-02-26 17:10:57 -07:00 |
|
tangxifan
|
60f40a9657
|
use constant module manager as much as possible in Verilog writer
|
2020-02-16 16:35:26 -07:00 |
|
tangxifan
|
11775c370b
|
bring FPGA top module verilog writer online. Fabric Verilog generator done
|
2020-02-16 16:18:14 -07:00 |
|
tangxifan
|
e37ac8a098
|
add grid module Verilog writer
|
2020-02-16 16:04:41 -07:00 |
|
tangxifan
|
c20caa1fa3
|
routing module Verilog writer is online
|
2020-02-16 14:47:54 -07:00 |
|
tangxifan
|
c6c3ef71f3
|
adapt all the Verilog submodule writers and bring it onlien
|
2020-02-16 13:35:18 -07:00 |
|
tangxifan
|
99c3712b6f
|
adapt Verilog wire module writer
|
2020-02-16 12:59:37 -07:00 |
|
tangxifan
|
5cc68b0730
|
adapt LUT Verilog writer
|
2020-02-16 12:45:58 -07:00 |
|
tangxifan
|
105ccabecc
|
adapt memroy writer for verilog
|
2020-02-16 12:41:43 -07:00 |
|
tangxifan
|
c9d8120ae0
|
adapt Verilog mux writer
|
2020-02-16 12:35:41 -07:00 |
|
tangxifan
|
a88c4bc954
|
add decode utils to libopenfpga and adapt local decoder writer in Verilog
|
2020-02-16 12:21:59 -07:00 |
|
tangxifan
|
3efd1a2a6d
|
print verilog module writer online
|
2020-02-16 12:04:03 -07:00 |
|
tangxifan
|
cf34339e96
|
adapt essential gates for submodule generation
|
2020-02-16 11:57:19 -07:00 |
|
tangxifan
|
2eba882332
|
put verilog submodules online. ready to bring the how submodule writer online
|
2020-02-16 11:41:20 -07:00 |
|
tangxifan
|
4cb61e2138
|
bring preprocessing flag Verilog netlists online
|
2020-02-16 00:03:24 -07:00 |
|
tangxifan
|
0d5292ad0d
|
adapt verilog writer utils
|
2020-02-15 23:26:59 -07:00 |
|
tangxifan
|
bf54be3d00
|
add option data structure for FPGA Verilog
|
2020-02-15 21:39:47 -07:00 |
|
tangxifan
|
8b0df8632c
|
bring fpga verilog create directory online
|
2020-02-15 20:38:45 -07:00 |
|
tangxifan
|
622c7826d1
|
start transplanting fpga_verilog
|
2020-02-15 15:03:00 -07:00 |