bring fpga verilog create directory online

openfpga/src/base/openfpga_context.h

@@ -10,6 +10,7 @@
 #include "mux_library.h"
 #include "tile_direct.h"
 #include "module_manager.h"
+#include "openfpga_flow_manager.h"
 #include "device_rr_gsb.h"
 
 /********************************************************************
@@ -50,6 +51,7 @@ class OpenfpgaContext : public Context  {
     const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; }
     const openfpga::TileDirect& tile_direct() const { return tile_direct_; }
     const openfpga::ModuleManager& module_graph() const { return module_graph_; }
+    const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
   public:  /* Public mutators */
     openfpga::Arch& mutable_arch() { return arch_; }
     openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@@ -60,6 +62,7 @@ class OpenfpgaContext : public Context  {
     openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; }
     openfpga::TileDirect& mutable_tile_direct() { return tile_direct_; }
     openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
+    openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
   private: /* Internal data */
     /* Data structure to store information from read_openfpga_arch library */
     openfpga::Arch arch_;
@@ -87,6 +90,9 @@ class OpenfpgaContext : public Context  {
 
     /* Fabric module graph */
     openfpga::ModuleManager module_graph_;
+ 
+    /* Flow status */
+    openfpga::FlowManager flow_manager_;
 };
 
 #endif

openfpga/src/base/openfpga_flow_manager.cpp

@@ -0,0 +1,26 @@
+/******************************************************************************
+ * Memember functions for data structure FlowManager
+ ******************************************************************************/
+#include "vtr_assert.h"
+
+#include "openfpga_flow_manager.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/**************************************************
+ * Public Accessors 
+ *************************************************/
+bool FlowManager::compress_routing() const {
+  return compress_routing_;
+}
+
+/******************************************************************************
+ * Private Mutators
+ ******************************************************************************/
+void FlowManager::set_compress_routing(const bool& enabled) {
+  compress_routing_ = enabled;
+}
+
+
+} /* end namespace openfpga */

openfpga/src/base/openfpga_flow_manager.h

@@ -0,0 +1,28 @@
+#ifndef FLOW_MANAGER_H
+#define FLOW_MANAGER_H
+
+/********************************************************************
+ * Include header files required by the data structure definition
+ *******************************************************************/
+/* Begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * FlowManager aims to resolve the dependency between OpenFPGA functional
+ * code blocks
+ * It can provide flags for downstream modules about if the data structures
+ * they require have already been constructed
+ *
+ *******************************************************************/
+class FlowManager {
+  public: /* Public accessors */
+    bool compress_routing() const;
+  public: /* Public mutators */
+    void set_compress_routing(const bool& enabled);
+  private: /* Internal Data */
+    bool compress_routing_;
+};
+
+} /* End namespace openfpga*/
+
+#endif

openfpga/src/base/openfpga_setup_command.cpp

@@ -135,7 +135,7 @@ void add_openfpga_setup_commands(openfpga::Shell<OpenfpgaContext>& shell) {
   shell.set_command_execute_function(shell_cmd_build_fabric_id, build_fabric);
   /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
   std::vector<ShellCommandId> cmd_dependency_build_fabric;
-  cmd_dependency_lut_truth_table_fixup.push_back(shell_cmd_link_openfpga_arch_id);
+  cmd_dependency_build_fabric.push_back(shell_cmd_link_openfpga_arch_id);
   shell.set_command_dependency(shell_cmd_build_fabric_id, cmd_dependency_build_fabric);
 } 
 

openfpga/src/base/openfpga_verilog_command.cpp

@@ -0,0 +1,51 @@
+/********************************************************************
+ * Add commands to the OpenFPGA shell interface, 
+ * in purpose of generate Verilog netlists modeling the full FPGA fabric
+ * This is one of the core engine of openfpga, including:
+ * - generate_fabric_verilog : generate Verilog netlists about FPGA fabric 
+ * - generate_fabric_verilog_testbench : TODO: generate Verilog testbenches 
+ *******************************************************************/
+#include "openfpga_verilog.h"
+#include "openfpga_verilog_command.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
+  /* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
+  const ShellCommandId& shell_cmd_build_fabric_id = shell.command(std::string("build_fabric"));
+
+  /* Add a new class of commands */
+  ShellCommandClassId openfpga_verilog_cmd_class = shell.add_command_class("FPGA-Verilog");
+
+  /******************************** 
+   * Command 'wirte_fabric_verilog' 
+   */
+  Command shell_cmd_write_fabric_verilog("write_fabric_verilog");
+  /* Add an option '--file' in short '-f'*/
+  CommandOptionId fabric_verilog_output_opt = shell_cmd_write_fabric_verilog.add_option("file", true, "Specify the output directory for Verilog netlists");
+  shell_cmd_write_fabric_verilog.set_option_short_name(fabric_verilog_output_opt, "f");
+  shell_cmd_write_fabric_verilog.set_option_require_value(fabric_verilog_output_opt, openfpga::OPT_STRING);
+  /* Add an option '--explicit_port_mapping' */
+  shell_cmd_write_fabric_verilog.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
+  /* Add an option '--include_timing' */
+  shell_cmd_write_fabric_verilog.add_option("include_timing", false, "Enable timing annotation in Verilog netlists");
+  /* Add an option '--include_signal_init' */
+  shell_cmd_write_fabric_verilog.add_option("include_signal_init", false, "Initialize all the signals in Verilog netlists");
+  /* Add an option '--support_icarus_simulator' */
+  shell_cmd_write_fabric_verilog.add_option("support_icarus_simulator", false, "Fine-tune Verilog netlists to support icarus simulator");
+  /* Add an option '--verbose' */
+  shell_cmd_write_fabric_verilog.add_option("verbose", false, "Enable verbose output");
+  
+  /* Add command 'write_fabric_verilog' to the Shell */
+  ShellCommandId shell_cmd_write_fabric_verilog_id = shell.add_command(shell_cmd_write_fabric_verilog, "generate Verilog netlists modeling full FPGA fabric");
+  shell.set_command_class(shell_cmd_write_fabric_verilog_id, openfpga_verilog_cmd_class);
+  shell.set_command_execute_function(shell_cmd_write_fabric_verilog_id, write_fabric_verilog);
+
+  /* The 'build_fabric' command should NOT be executed before 'link_openfpga_arch' */
+  std::vector<ShellCommandId> cmd_dependency_write_fabric_verilog;
+  cmd_dependency_write_fabric_verilog.push_back(shell_cmd_build_fabric_id);
+  shell.set_command_dependency(shell_cmd_write_fabric_verilog_id, cmd_dependency_write_fabric_verilog);
+} 
+
+} /* end namespace openfpga */

openfpga/src/base/openfpga_verilog_command.h

@@ -0,0 +1,21 @@
+#ifndef OPENFPGA_VERILOG_COMMAND_H
+#define OPENFPGA_VERILOG_COMMAND_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "shell.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell); 
+
+} /* end namespace openfpga */
+
+#endif

openfpga/src/fpga_verilog/verilog_api.cpp

@@ -40,17 +40,17 @@ namespace openfpga {
  * 7. Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module. This testbench is created for quick verification and formal verification purpose.
  * 8. Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
  ********************************************************************/
-void fabric_verilog(ModuleManager& module_manager,
-                    const CircuitLibrary& circuit_lib,
-                    const MuxLibrary& mux_lib,
-                    const DeviceGrid& grids, 
-                    const DeviceRRGSB& device_rr_gsb,
-                    const std::string& output_directory,
-                    const bool& compress_routing,
-                    const bool& dump_explict_verilog,
-                    const bool& verbose) {
+void fpga_fabric_verilog(const ModuleManager& module_manager,
+                         const CircuitLibrary& circuit_lib,
+                         const MuxLibrary& mux_lib,
+                         const DeviceGrid& grids, 
+                         const DeviceRRGSB& device_rr_gsb,
+                         const std::string& output_directory,
+                         const bool& compress_routing,
+                         const bool& dump_explict_verilog,
+                         const bool& verbose) {
 
-  vtr::ScopedStartFinishTimer timer("Generate Verilog netlists for FPGA fabric\n");
+  vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n");
 
   std::string src_dir_path = format_dir_path(output_directory);
 

openfpga/src/fpga_verilog/verilog_api.h

@@ -21,15 +21,15 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void fabric_verilog(ModuleManager& module_manager,
-                    const CircuitLibrary& circuit_lib,
-                    const MuxLibrary& mux_lib,
-                    const DeviceGrid& grids, 
-                    const DeviceRRGSB& device_rr_gsb,
-                    const std::string& output_directory,
-                    const bool& compress_routing,
-                    const bool& dump_explict_verilog,
-                    const bool& verbose);
+void fpga_fabric_verilog(const ModuleManager& module_manager,
+                         const CircuitLibrary& circuit_lib,
+                         const MuxLibrary& mux_lib,
+                         const DeviceGrid& grids, 
+                         const DeviceRRGSB& device_rr_gsb,
+                         const std::string& output_directory,
+                         const bool& compress_routing,
+                         const bool& dump_explict_verilog,
+                         const bool& verbose);
 
 } /* end namespace openfpga */
 

openfpga/src/main.cpp

@@ -12,6 +12,7 @@
 /* Header file from openfpga */
 #include "vpr_command.h"
 #include "openfpga_setup_command.h"
+#include "openfpga_verilog_command.h"
 #include "basic_command.h"
 
 #include "openfpga_title.h"
@@ -52,6 +53,9 @@ int main(int argc, char** argv) {
   /* Add openfpga setup commands */
   openfpga::add_openfpga_setup_commands(shell);
 
+  /* Add openfpga verilog commands */
+  openfpga::add_openfpga_verilog_commands(shell);
+
   /* Add basic commands: exit, help, etc. 
    * Note:
    * This MUST be the last command group to be added! 

openfpga/test_script/s298_k6_frac.openfpga

@@ -21,5 +21,9 @@ lut_truth_table_fixup #--verbose
 #  - Enable pin duplication on grid modules 
 build_fabric --compress_routing --duplicate_grid_pin --verbose
 
+# Write the Verilog netlit for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
+
 # Finish and exit OpenFPGA
 exit