tangxifan
|
bcc16d732c
|
[Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches
|
2021-06-25 10:10:16 -06:00 |
|
tangxifan
|
67dec810eb
|
[Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes
|
2021-06-24 17:27:32 -06:00 |
|
tangxifan
|
549657e1fb
|
[Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base
|
2021-06-24 17:13:36 -06:00 |
|
tangxifan
|
21d1519658
|
[Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option
|
2021-06-24 16:56:28 -06:00 |
|
tangxifan
|
fed975c52a
|
[Tool] Add postfix removal support in write_io_mapping command
|
2021-06-18 16:13:50 -06:00 |
|
tangxifan
|
d9d57aad42
|
[Tool] Added default net type options to verilog testbench generator command
|
2021-06-14 11:37:49 -06:00 |
|
tangxifan
|
7ade48343c
|
[Tool] Deprecate command 'write_verilog_testbench'
|
2021-06-09 17:06:01 -06:00 |
|
tangxifan
|
97396eda2b
|
[Tool] Add a new command 'write_simulation_task_info'
|
2021-06-08 22:10:02 -06:00 |
|
tangxifan
|
d2275b971d
|
[Tool] Add a new command 'write_preconfigured_testbench'
|
2021-06-08 21:53:51 -06:00 |
|
tangxifan
|
85679c0fe2
|
[Tool] Bug fix in the top testbench switch due to fast configuration
|
2021-06-08 21:32:26 -06:00 |
|
tangxifan
|
8db19c7af9
|
[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
|
2021-06-08 21:28:16 -06:00 |
|
tangxifan
|
5075c68418
|
[Tool] Remove duplicated codes on fast configuration
|
2021-06-08 20:58:04 -06:00 |
|
tangxifan
|
4aef9d5c96
|
[Tool] Remove redundant codes
|
2021-06-07 21:54:01 -06:00 |
|
tangxifan
|
366dcff75d
|
[Tool] Now 'write_full_testbench' supports flatten(vanilla) configuration protocol
|
2021-06-07 21:49:31 -06:00 |
|
tangxifan
|
9808b61b36
|
[Tool] Bug fix on the unfit vector size of bit index register in Verilog testbench in some cases
|
2021-06-07 20:06:39 -06:00 |
|
tangxifan
|
ba75c18378
|
[Tool] Now 'write_full_testbench' supports memory bank configuration protocol
|
2021-06-07 17:40:07 -06:00 |
|
tangxifan
|
1a5902ca74
|
[Tool] Bug fix in finding pruned bitstream for frame-based protocol when fast configuration is enabled
|
2021-06-07 14:32:56 -06:00 |
|
tangxifan
|
af298de121
|
[Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol
|
2021-06-07 13:53:32 -06:00 |
|
tangxifan
|
d644b8f22d
|
[Tool] Support external bitstream file when generating full testbench for frame-based decoder
|
2021-06-07 11:55:11 -06:00 |
|
tangxifan
|
d98be9f87b
|
[Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog
|
2021-06-04 16:45:00 -06:00 |
|
tangxifan
|
6e69c2d70a
|
[Tool] Patch fast configuration in full Verilog testbench generator
|
2021-06-04 16:34:55 -06:00 |
|
tangxifan
|
98308133c1
|
[Tool] Add configuration skip capability to top testbench which loads external bitstream file
|
2021-06-04 11:24:05 -06:00 |
|
tangxifan
|
adb18d28b8
|
[Tool] Remove unused arguments
|
2021-06-04 10:37:28 -06:00 |
|
tangxifan
|
ae6a46cd60
|
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
|
2021-06-03 15:41:11 -06:00 |
|
tangxifan
|
0b49c22682
|
[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
|
2021-04-18 16:11:11 -06:00 |
|
tangxifan
|
6550ea3dfa
|
[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
|
2021-04-18 12:02:49 -06:00 |
|
tangxifan
|
6e9b24f9bf
|
[Tool] Patch the invalid pin constraint net name
|
2021-04-17 19:56:30 -06:00 |
|
tangxifan
|
253422e7b7
|
[Tool] Bugfix due to refactoring
|
2021-04-17 19:27:03 -06:00 |
|
tangxifan
|
02ca51d84b
|
[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes
|
2021-04-17 17:45:50 -06:00 |
|
tangxifan
|
d95a1e2776
|
[Tool] Encapulate search function in PinConstraint data structure
|
2021-04-17 17:31:55 -06:00 |
|
tangxifan
|
da619fabe7
|
[Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench
|
2021-04-17 17:19:34 -06:00 |
|
tangxifan
|
6e1b58f8a6
|
[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports
|
2021-04-17 15:05:22 -06:00 |
|
tangxifan
|
4b8f5f294a
|
[Tool] Capsulate fabric bitstream organization for configuration chain
|
2021-04-10 14:28:31 -06:00 |
|
tangxifan
|
afa0e751da
|
[Tool] Use alias for complex bitstream data types
|
2021-04-10 14:12:02 -06:00 |
|
tangxifan
|
fa11410425
|
[Tool] Remove exceptions on outputing verilog port with lsb=0
|
2021-03-17 20:27:08 -06:00 |
|
tangxifan
|
521e1850c8
|
[Tool] Correct syntax errors for timing definition in verilog for iverilog 10.1
|
2021-02-28 17:04:27 -07:00 |
|
tangxifan
|
73461971d2
|
[Tool] Bug fix for printing single-bit ports in Verilog netlists
|
2021-02-28 16:12:57 -07:00 |
|
tangxifan
|
15e26a5602
|
[Tool] Support default_net_type Verilog syntex in fabric generator
|
2021-02-28 11:57:40 -07:00 |
|
tangxifan
|
d2defebee9
|
[Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
|
2021-01-22 16:42:13 -07:00 |
|
tangxifan
|
3f80a26172
|
[Tool] Bug fix for combinational benchmarks in pre-config testbench generation
|
2021-01-19 18:22:50 -07:00 |
|
tangxifan
|
75b99b78e9
|
[Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks
|
2021-01-19 17:38:51 -07:00 |
|
tangxifan
|
da200658c1
|
[Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks
|
2021-01-19 17:29:59 -07:00 |
|
tangxifan
|
0670c2de59
|
[Tool] Deploy pin constraints to preconfig Verilog module generation
|
2021-01-19 16:56:30 -07:00 |
|
tangxifan
|
87b2c1f3b8
|
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
|
2021-01-15 12:01:53 -07:00 |
|
tangxifan
|
852f5bb72e
|
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
|
2021-01-14 15:38:24 -07:00 |
|
tangxifan
|
9cc9e45b4b
|
[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
|
2021-01-13 15:13:19 -07:00 |
|
tangxifan
|
d11a3d9fef
|
[Tool] Avoid outputting signal initialization codes because they are bulky
|
2020-12-06 14:29:16 -07:00 |
|
tangxifan
|
6bdfcb0147
|
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
|
2020-12-05 12:44:09 -07:00 |
|
tangxifan
|
6f18688f0e
|
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
|
2020-12-05 10:53:01 -07:00 |
|
tangxifan
|
0da92ad888
|
[Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules
|
2020-12-04 22:16:51 -07:00 |
|
tangxifan
|
5be9e9b736
|
[Tool] Adapted tools to support I/O in center grid
|
2020-12-04 18:50:13 -07:00 |
|
tangxifan
|
4aa6264b1c
|
[Tool] Rework simulation time period to be sync with actual stimuli
|
2020-12-02 22:58:13 -07:00 |
|
tangxifan
|
c82f01b3ab
|
[Tool] Use conditional operator in signal initialization to eliminate all the warning messages
|
2020-11-23 15:50:23 -07:00 |
|
tangxifan
|
e644545f21
|
[Doc] Remove signal initialization for select ports of MUXes and Pass-gates; Use urandom to generate just-fit random vectors
|
2020-11-23 15:02:06 -07:00 |
|
tangxifan
|
3b2a4c5387
|
[Tool] Add signal initialization to Verilog testbench generator and remove it from fabric netlists
|
2020-11-22 20:25:03 -07:00 |
|
tangxifan
|
57a24570f5
|
[Tool] Move icarus and signal initialization options to testbench generator
|
2020-11-22 16:01:31 -07:00 |
|
tangxifan
|
dcb50e4f19
|
[Tool] Use use standard data structure to store global port information
|
2020-11-10 19:07:28 -07:00 |
|
tangxifan
|
ba0120bd76
|
[Tool] Remove the limitation on requiring Qb ports for CCFF
|
2020-11-06 11:10:04 -07:00 |
|
tangxifan
|
37c10f0cb5
|
[Tool] Add mappable I/O support and enhance I/O support
|
2020-11-04 20:21:49 -07:00 |
|
tangxifan
|
1e47203c7c
|
[Tool] Auto-generated gate Verilog netlist should not contain any signal initalization
|
2020-11-02 18:35:26 -07:00 |
|
tangxifan
|
e4d974c5c8
|
[Tool] Split io location mapping builder from fabric builder
|
2020-11-02 18:27:34 -07:00 |
|
tangxifan
|
b78f8bec16
|
[Tool] Bug fixed for multi-region configuration frame
|
2020-10-30 21:19:20 -06:00 |
|
tangxifan
|
5bcd559851
|
[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
|
2020-10-30 17:29:04 -06:00 |
|
tangxifan
|
0d77916041
|
[Tool] Support multi-region frame-based configuration protocol
|
2020-10-30 10:43:11 -06:00 |
|
tangxifan
|
987eccf586
|
[Tool] Bug fix in multi-region memory bank; Basic test passed
|
2020-10-29 16:26:45 -06:00 |
|
tangxifan
|
448e88645a
|
[Tool] Support multiple memory banks in top-level module
|
2020-10-29 12:42:03 -06:00 |
|
tangxifan
|
1ef0898f41
|
[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
|
2020-10-12 12:31:51 -06:00 |
|
tangxifan
|
e988e35f81
|
[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
|
2020-09-29 12:22:10 -06:00 |
|
tangxifan
|
154f23b108
|
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches
|
2020-09-26 11:54:06 -06:00 |
|
tangxifan
|
1b4e449179
|
[OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol
|
2020-09-25 21:05:20 -06:00 |
|
tangxifan
|
6bea712db0
|
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
|
2020-09-25 14:54:51 -06:00 |
|
tangxifan
|
8468f25b23
|
[OpenFPGA Tool] Bug fix in the smart fast configuration strategy
|
2020-09-24 16:31:55 -06:00 |
|
tangxifan
|
46b12611a9
|
[OpenFPGA Tool] Bug fix for smart fast configuration
|
2020-09-23 22:04:07 -06:00 |
|
tangxifan
|
154c9045f6
|
[OpoenFPGA Tool] Bug fix for smart fast configuration
|
2020-09-23 21:38:42 -06:00 |
|
tangxifan
|
c2c37d7555
|
[OpenFPGA Tool] Add more print-out for smart fast configuration
|
2020-09-23 21:34:23 -06:00 |
|
tangxifan
|
a3abf81afe
|
[OpenFPGA Tool] Support on set signals and smart selection between reset and set signal for fast configuration
|
2020-09-23 21:25:06 -06:00 |
|
tangxifan
|
064678fe32
|
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
|
2020-09-23 20:27:52 -06:00 |
|
tangxifan
|
ad881ea4dc
|
[OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank
|
2020-09-23 18:59:25 -06:00 |
|
tangxifan
|
460fef5807
|
[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
|
2020-09-20 12:58:55 -06:00 |
|
tangxifan
|
0f25b52907
|
[FPGA-Verilog] code format fix
|
2020-09-20 12:18:22 -06:00 |
|
tangxifan
|
2603836111
|
split logical tile netlists to keep good Verilog hierarchy
|
2020-07-24 12:53:21 -06:00 |
|
tangxifan
|
be5966475e
|
formulate file name, module name and instance name to be consistent
|
2020-07-24 12:23:27 -06:00 |
|
tangxifan
|
22159531c5
|
bug fix in power gating support of FPGA-Verilog
|
2020-07-22 20:21:38 -06:00 |
|
tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
|
tangxifan
|
eb070694b5
|
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
|
2020-07-15 17:52:41 -06:00 |
|
tangxifan
|
66a50742fc
|
use configuration chain in the k4k4 test case to speed up CI
|
2020-07-15 11:56:11 -06:00 |
|
tangxifan
|
3f14fe62c7
|
add fast configuration support for configuration chain protocol
|
2020-07-15 11:44:23 -06:00 |
|
tangxifan
|
1ad6e8292a
|
move constants from verilog domain to common so that FPGA-SPICE can share
|
2020-07-05 11:39:46 -06:00 |
|
tangxifan
|
7c2a0a6ad2
|
streamline fabric verilog options
|
2020-07-05 11:28:14 -06:00 |
|
tangxifan
|
6ea857ae6c
|
use fast method to inquire number of bits and blocks in bitstream databases
|
2020-07-03 10:55:25 -06:00 |
|
tangxifan
|
9f19c36a89
|
use char in fabric bitstream to save memory footprint
|
2020-07-02 15:56:50 -06:00 |
|
tangxifan
|
ac22ba28e4
|
add config protocol type information to simulation ini file
|
2020-07-02 12:26:59 -06:00 |
|
tangxifan
|
cb2baed257
|
bug fix in simulation ini GPIO width
|
2020-07-01 13:39:12 -06:00 |
|
tangxifan
|
b74dde919d
|
add additional information in the simulation ini file for UVM
|
2020-07-01 13:07:39 -06:00 |
|
tangxifan
|
e9937954f2
|
optimizing the constant writing in Verilog for single bits
|
2020-06-29 12:29:25 -06:00 |
ganeshgore
|
559564c333
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2020-06-12 17:31:14 -06:00 |
|
tangxifan
|
3c10af7f2b
|
bug fixed in memory bank configuration protocol which is due to the wrong Verilog port merging algorithm
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
8267dad8ef
|
add decoder support for Z signals
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
5368485bd6
|
keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
c85ccceac7
|
try bug fixing in memory bank configuration protocol
|
2020-06-11 19:31:14 -06:00 |