Emin Cetin
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6c2c4e8b14
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adding comment
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2022-01-28 08:57:45 +03:00 |
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Emin Cetin
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f9b47c3b34
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missing semicolon
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2022-01-27 16:49:04 +03:00 |
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Emin Cetin
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8f7ee4e338
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changing condition of bitstream downloading
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2022-01-27 11:49:55 +03:00 |
tangxifan
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62b57b05d2
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[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
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2022-01-25 12:09:08 -08:00 |
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tangxifan
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ff264c00a2
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
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2021-10-31 11:51:34 -07:00 |
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tangxifan
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91627abe12
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[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided
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2021-10-30 11:53:46 -07:00 |
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tangxifan
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546350ae41
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[FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks
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2021-10-10 23:19:39 -07:00 |
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tangxifan
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202b50c0e3
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[FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why
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2021-10-10 20:57:23 -07:00 |
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tangxifan
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de3275e9ba
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[FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains
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2021-10-10 16:56:07 -07:00 |
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tangxifan
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6aa4991314
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[FPGA-Verilog] Bug fix
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2021-10-09 21:34:07 -07:00 |
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tangxifan
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34575f7222
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[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
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2021-10-09 20:39:45 -07:00 |
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tangxifan
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19a551e641
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[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
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2021-10-09 16:44:04 -07:00 |
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tangxifan
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8f5f30792f
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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tangxifan
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54a8809b3c
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[FPGA-Verilog] Bug fix in computing clock frequency for shift register chains
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2021-10-06 16:49:28 -07:00 |
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tangxifan
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27153bbc89
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[FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition
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2021-10-06 13:38:51 -07:00 |
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tangxifan
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bf473f50f8
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[FPGA-Verilog] Correct bugs in logging clock frequencies
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2021-10-06 11:55:57 -07:00 |
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tangxifan
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fcb5470baa
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[Lib] Add validator to check if a clock is constrained in simulation settings
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2021-10-06 11:48:23 -07:00 |
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tangxifan
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82ed6b177b
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[FPGA-Verilog] Now consider clock constraints for BL/WL shift registers
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2021-10-06 11:39:28 -07:00 |
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tangxifan
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2badcb58f2
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[FPGA-Verilog] Fixed a critical bug in verilog testbench generator for QL memory bank using BL/WL register which causes misalignment in shift register loading
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2021-10-03 16:04:47 -07:00 |
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tangxifan
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756b4c7dc8
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[FPGA-Verilog] Bug fix in estimating the simulation period for QuickLogic memory bank using BL/WL shift registers
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2021-10-03 12:11:20 -07:00 |
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tangxifan
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3eb601531a
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[FPGA-Verilog] Many bug fixes
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2021-10-02 23:39:53 -07:00 |
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tangxifan
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d453e6477d
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[FPGA-Verilog] Bug fix
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2021-10-02 22:32:57 -07:00 |
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tangxifan
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02af633acd
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[FPGA-Verilog] Fixed several bugs in testbench generator which caused iVerilog errors
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2021-10-02 22:14:15 -07:00 |
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tangxifan
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fa7e168137
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[FPGA-Verilog] Now testbench generator connects global shift register clocks to FPGA ports
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2021-10-02 22:08:14 -07:00 |
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tangxifan
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76d58ebaa0
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[FPGA-Verilog] Move clock generator to generic stimuli and shift register clock period is auto tuned by programming clock period
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2021-10-02 21:48:10 -07:00 |
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tangxifan
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54ec74d8d2
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[FPGA-Verilog] Bug fix in code generator
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2021-10-02 17:31:37 -07:00 |
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tangxifan
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32fc0a1692
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[FPGA-Verilog] Upgrading verilog testbench generator for QuickLogic memory bank using BL/WL shift register
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2021-10-02 17:25:27 -07:00 |
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tangxifan
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9e5debabe1
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[FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks
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2021-10-01 16:23:38 -07:00 |
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tangxifan
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2bd2788e77
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[Engine] Upgrading testbench generator to support QuickLogic memory bank with shift registers
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2021-10-01 11:23:40 -07:00 |
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tangxifan
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7b010ba0f4
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[Engine] Support programming shift register clock in XML syntax
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2021-10-01 11:00:38 -07:00 |
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tangxifan
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2d4c200d58
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[FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists
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2021-09-29 20:56:02 -07:00 |
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tangxifan
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29c351f5a4
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[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator
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2021-09-25 19:34:21 -07:00 |
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tangxifan
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a56d1f4fdb
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[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
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2021-09-25 17:49:15 -07:00 |
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tangxifan
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c84c0d4a3f
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[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
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2021-09-20 17:07:26 -07:00 |
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tangxifan
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b787c4e100
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[Engine] Register QL memory bank as a legal protocol
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2021-09-09 15:06:51 -07:00 |
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tangxifan
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1aac3197eb
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[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
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2021-09-05 21:38:00 -07:00 |
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tangxifan
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e9d29e27e5
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[Tool] Bug fix
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2021-07-02 15:32:30 -06:00 |
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tangxifan
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6e6c3e9fa4
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[Tool] Patch the critical bug in the use of signal polarity in pin constraints
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2021-07-02 15:26:21 -06:00 |
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tangxifan
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9074bffa68
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[Tool] Support customized default value in pin constraint file
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2021-07-01 23:43:19 -06:00 |
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tangxifan
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d0e4f8521f
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[Tool] Bug fix on the reset stimuli
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2021-07-01 19:58:54 -06:00 |
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tangxifan
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b5df1f9aeb
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[Tool] Bug fix for redundant endif in netlists
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2021-06-29 17:02:16 -06:00 |
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tangxifan
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b83eef47b4
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[Tool] Bug fix for testbench generation without self checking codes
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2021-06-29 16:27:29 -06:00 |
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tangxifan
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6a260cadbf
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[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
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2021-06-29 15:42:23 -06:00 |
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tangxifan
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7ac7de789e
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[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
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2021-06-29 15:26:40 -06:00 |
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tangxifan
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77dddaeb39
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[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions
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2021-06-29 14:26:33 -06:00 |
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tangxifan
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a3208b332b
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[Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
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2021-06-29 11:50:53 -06:00 |
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tangxifan
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dfe1db996a
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[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time
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2021-06-29 09:56:04 -06:00 |
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tangxifan
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87446a14c3
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[Tool] Bug fix for the option ``--embed_bitstream none``
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2021-06-27 19:45:06 -06:00 |
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tangxifan
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90163fab6c
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[Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>'
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2021-06-25 15:06:07 -06:00 |
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tangxifan
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2bb514c51a
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[Tool] Support time unit in writing simulation information file
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2021-06-25 10:33:29 -06:00 |