tangxifan
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e37ac8a098
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add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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tangxifan
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c20caa1fa3
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routing module Verilog writer is online
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2020-02-16 14:47:54 -07:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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99c3712b6f
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adapt Verilog wire module writer
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2020-02-16 12:59:37 -07:00 |
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tangxifan
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5cc68b0730
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adapt LUT Verilog writer
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2020-02-16 12:45:58 -07:00 |
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tangxifan
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105ccabecc
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adapt memroy writer for verilog
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2020-02-16 12:41:43 -07:00 |
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tangxifan
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c9d8120ae0
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adapt Verilog mux writer
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2020-02-16 12:35:41 -07:00 |
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tangxifan
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a88c4bc954
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add decode utils to libopenfpga and adapt local decoder writer in Verilog
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2020-02-16 12:21:59 -07:00 |
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tangxifan
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3efd1a2a6d
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print verilog module writer online
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2020-02-16 12:04:03 -07:00 |
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tangxifan
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cf34339e96
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adapt essential gates for submodule generation
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2020-02-16 11:57:19 -07:00 |
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tangxifan
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2eba882332
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put verilog submodules online. ready to bring the how submodule writer online
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2020-02-16 11:41:20 -07:00 |
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tangxifan
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4cb61e2138
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bring preprocessing flag Verilog netlists online
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2020-02-16 00:03:24 -07:00 |
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tangxifan
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0d5292ad0d
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adapt verilog writer utils
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2020-02-15 23:26:59 -07:00 |
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tangxifan
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bf54be3d00
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add option data structure for FPGA Verilog
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2020-02-15 21:39:47 -07:00 |
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tangxifan
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8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
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622c7826d1
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start transplanting fpga_verilog
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2020-02-15 15:03:00 -07:00 |