7ade48343c
[Tool] Deprecate command 'write_verilog_testbench'
2021-06-09 17:06:01 -06:00
2299ce3157
[Tool] Preconfigured testbench writer now supports icarus simulator
2021-06-09 13:49:25 -06:00
3bc8e760db
[Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command
2021-06-09 11:14:45 -06:00
89fb672631
[Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use
2021-06-09 10:49:00 -06:00
97396eda2b
[Tool] Add a new command 'write_simulation_task_info'
2021-06-08 22:10:02 -06:00
d2275b971d
[Tool] Add a new command 'write_preconfigured_testbench'
2021-06-08 21:53:51 -06:00
8db19c7af9
[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
2021-06-08 21:28:16 -06:00
061f832429
[Tool] Enable fast configuration when writing fabric bitstream
2021-06-04 16:23:40 -06:00
81048d3698
[Tool] Add option '--fast_configuration' to 'write_full_testbench' command
2021-06-04 11:26:39 -06:00
ae6a46cd60
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
2021-06-03 15:41:11 -06:00
c4ecc9ee7c
[Tool] Patch data type of report bitstream distribution command-line option
2021-05-07 11:44:01 -06:00
db9bb9124e
[Tool] Add report bitstream distribution command to openfpga shell
2021-05-07 11:41:25 -06:00
43c1e052ef
[Tool] Add a writer to output I/O mapping information to XML files
2021-04-27 14:30:16 -06:00
56948244bc
[Tool] Patch a critical bug in pb pin fixup
2021-04-22 16:19:54 -06:00
0aec30bac6
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
2021-04-19 15:53:33 -06:00
c8d41b4e69
[Tool] Change routing module port naming to include architecture port names
2021-03-14 19:35:49 -06:00
956b9aca01
[Tool] Trim dead codes in port naming function
2021-03-13 20:23:08 -07:00
2c5634ee76
[Tool] Change pin naming of grid modules to be related to architecture port names
2021-03-13 20:05:18 -07:00
15e26a5602
[Tool] Support default_net_type Verilog syntex in fabric generator
2021-02-28 11:57:40 -07:00
aae03482f5
[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
2021-02-18 19:37:17 -07:00
0c409b5bcc
[Tool] Add bitstream annotation support
2021-02-01 20:49:36 -07:00
f102e84497
[Tool] Add bitstream setting file to openfpga library
2021-02-01 17:43:46 -07:00
4b77a3a574
[Tool] Now activity file is not a manadatory input of openfpga tools
2021-01-29 11:33:40 -07:00
d9fda31a9f
[Tool] Add --version to openfpga shell option and a command to openfpga shell
2021-01-27 16:03:46 -07:00
4cc8b08a6c
[Tool] Add openfpga version display
2021-01-23 16:38:00 -07:00
0670c2de59
[Tool] Deploy pin constraints to preconfig Verilog module generation
2021-01-19 16:56:30 -07:00
bb8e7e25c2
[Tool] Start deploying design constraints in repack engine
2021-01-16 21:27:12 -07:00
fa67517349
[Tool] Add repack design constraints to openfpga command 'repack'
2021-01-16 18:49:34 -07:00
87b2c1f3b8
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
2021-01-15 12:01:53 -07:00
852f5bb72e
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
2021-01-14 15:38:24 -07:00
cc91a0aebd
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
2021-01-04 17:14:26 -07:00
6bdfcb0147
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
2020-12-05 12:44:09 -07:00
6f18688f0e
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
2020-12-05 10:53:01 -07:00
5be9e9b736
[Tool] Adapted tools to support I/O in center grid
2020-12-04 18:50:13 -07:00
73aaa261d8
[Tool] Relax the IO restriction in pb_pin post-routing packing fix-up
2020-12-04 17:55:25 -07:00
b661c39b04
[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
2020-12-02 19:36:36 -07:00
57a24570f5
[Tool] Move icarus and signal initialization options to testbench generator
2020-11-22 16:01:31 -07:00
372fb261fd
[Tool] Extend the support on global tile port for I/O tiles
2020-11-11 15:09:40 -07:00
9cbc374b33
[Tool] Add check codes for tile annotation
2020-11-11 12:03:13 -07:00
81e56d45d6
[Tool] Update FPGA-SDC to use the new data structure for global ports
2020-11-10 21:17:17 -07:00
c61ec5a8b8
[Tool] Bug fix for defining global ports from tiles
2020-11-10 20:31:14 -07:00
dcb50e4f19
[Tool] Use use standard data structure to store global port information
2020-11-10 19:07:28 -07:00
e4d974c5c8
[Tool] Split io location mapping builder from fabric builder
2020-11-02 18:27:34 -07:00
1ef0898f41
[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
2020-10-12 12:31:51 -06:00
721bcce373
[Tool] Change analysis SDC file name to track netlist name
2020-10-10 17:43:35 -06:00
e179a58b15
[OpenFPGA Tool] Bug fix for long runtime
2020-09-28 20:42:18 -06:00
064678fe32
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
2020-09-23 20:27:52 -06:00
1dfb3e06cc
[FPGA-SPICE] add SPICE writer for logic blocks
2020-09-20 12:38:24 -06:00
5e78e91fdf
[FPGA-SPICE] Add SPICE writer for routing blocks
2020-09-20 12:27:48 -06:00
0f9fce92b2
[FPGA-SPICE] Add SPICE writer for routing multiplexers
2020-09-20 11:49:02 -06:00
9cfb2f52ef
[OpenFPGA code] bug fix for fully equivalent outputs of pb_type
2020-09-16 19:26:46 -06:00
fc6bfdc7a2
[OpenFPGA Code] Patch syntax compatibility for older gcc
2020-09-14 18:55:21 -06:00
5d83abb2cf
bug fix in read architecture bitstream and regression tests
2020-07-27 19:37:05 -06:00
6592db3dfe
bug fix in calling the wrong function of write_fabric_bitstream
2020-07-27 14:32:58 -06:00
d68e77f322
Split the writer of build_fabric_bitstream to a separated command so that users will output multiple files in different formats
2020-07-27 14:16:33 -06:00
5fb7d9fbdb
bug fix in fabric bitstream file format writer
2020-07-26 21:28:45 -06:00
92d2d2d849
add fabric bitstream XML writer
2020-07-26 21:00:57 -06:00
2603836111
split logical tile netlists to keep good Verilog hierarchy
2020-07-24 12:53:21 -06:00
be5966475e
formulate file name, module name and instance name to be consistent
2020-07-24 12:23:27 -06:00
b5fd6aa859
add inverter subckt writer to FPGA-SPICE
2020-07-17 13:01:08 -06:00
824b56f14c
fabric key can now accept instance name only; decoders are no longer part of the key
2020-07-06 16:42:33 -06:00
462fc0d04e
add spice transistor wrapper writer
2020-07-05 14:50:29 -06:00
81171a8f97
start transplanting FPGA-SPICE
2020-07-05 12:10:12 -06:00
1f38e17111
bug fix for naming conflicts in mux local encoder and architecture decoders
2020-07-03 14:12:13 -06:00
adee87569d
enable fast bitstream building by creating a frame view of fabric
2020-07-02 16:25:36 -06:00
0a3c746fb1
now split CB module bus ports into lower/upper parts
2020-07-01 14:37:13 -06:00
e688ca1388
update fabric bitstream writer to support various configuration protocols
2020-07-01 11:54:28 -06:00
2e7684b746
adapt bus ports in connection block module builder
2020-06-30 17:50:53 -06:00
2ef083c49d
adapt SB module builder to use bus ports
2020-06-30 16:02:40 -06:00
ebf5636e7b
add verbose output to edge sorting for GSBs
2020-06-26 17:10:51 -06:00
aded675633
rename files in fpga bitstream library to be consistent with conventions
2020-06-21 13:06:39 -06:00
d526f08782
deploy bitstream reader in openfpga shell
2020-06-20 18:48:19 -06:00
675a59ecb8
Move fpga_bitstream to the libopenfpga library and add XML reader
2020-06-20 18:25:17 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
b91c30191a
add input and output net echo in arch bitstream database
2020-06-17 00:04:55 -06:00
a5055e9d26
add support about loading external fabric key
2020-06-12 13:03:11 -06:00
9dbf536306
add shuffled configurable children support for top module
2020-06-12 11:16:53 -06:00
3499b4d3e7
add fabric key writer for top-level module
2020-06-12 10:41:34 -06:00
278acee216
bug fix for 'build_fabric' command
2020-06-11 23:59:24 -06:00
9167b288b6
add options for fabric key
2020-06-11 21:50:46 -06:00
58807bfcb3
remove simulation settings from openfpga arch data structure
2020-06-11 19:31:16 -06:00
96b58dfdbb
use new simulation setting command in openfpga shell
2020-06-11 19:31:15 -06:00
4a2f6dfae2
add read/write simulation setting commands to openfpga shell
2020-06-11 19:31:15 -06:00
0bee70bee6
finish memory bank configuration protocol support.
2020-06-11 19:31:13 -06:00
0e16ee1030
add configuration bus nets for memory bank decoders at top module
2020-06-11 19:31:13 -06:00
fa8dfc1fbd
add configuration protocol ports to top module for memory bank organization
2020-06-11 19:31:13 -06:00
fbe05963e0
add configuration bus builder for flatten memory organization (applicable to memory bank and standalone configuration protocol)
2020-06-11 19:31:12 -06:00
d2d443a988
start developing memory bank and standalone configuration protocol
2020-06-11 19:31:12 -06:00
8b3e79766c
add fast configuration option to fpga_verilog to speed up full testbench simulation
2020-06-11 19:31:12 -06:00
65df309419
bug fixing for frame-based configuration protocol and rename some naming function to be generic
2020-06-11 19:31:10 -06:00
4a0e1cd908
add fabric bitstream data structure and deploy it to Verilog testbench generation
2020-06-11 19:31:10 -06:00
5c5a044c68
add architecture decoder (for frame-based config memory) to Verilog writer
2020-06-11 19:31:09 -06:00
290dd1a8a6
add frame decoder builder to all the module graph builder except the top-level
2020-06-11 19:31:09 -06:00
8864920460
add frame-based memory module builder
2020-06-11 19:31:09 -06:00
3a26bb5eef
add advanced check in configurable memories
2020-06-11 19:31:09 -06:00
bba476fef4
add explicit port mapping support to Verilog testbench generator
2020-06-11 19:31:07 -06:00
e089b0ef22
use constant string for inverted port naming
2020-06-11 19:31:07 -06:00
8915d10d27
add verbose output option to configure port disable timing writer
2020-06-11 19:31:07 -06:00
f52b5d5b4c
use error code in read_arch command
2020-06-11 19:31:07 -06:00
e9ceedb01b
use constant openfpga context in SDC generator
2020-06-11 19:31:07 -06:00
13f591cacf
add new command to disable timing for configure ports of programmable modules
2020-06-11 19:31:06 -06:00
4c0953415b
add configuration chain sdc writer
2020-06-11 19:31:06 -06:00
8d2360a710
simplify include_netlist.v
2020-06-11 19:31:05 -06:00
5a8c05378e
add --depth option to fabric hierarchy writer
2020-06-11 19:31:04 -06:00
d9dc7160a7
minor fix on the hierarchy writer in SDC generator
2020-06-11 19:31:04 -06:00
c651df6421
add hierarchy writer to SDC generator
2020-06-11 19:31:04 -06:00
6aff33dd35
add fabric hierarchy writer
2020-06-11 19:31:04 -06:00
8726c618eb
add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
2020-06-11 19:31:03 -06:00
7e82c23f52
now add SDC generator supports both hierarchical and flatten in writing timing constraints
2020-06-11 19:31:03 -06:00
d0793d9029
now disable_sb_output support wildcard
2020-06-11 19:31:02 -06:00
8695c5ee78
add options to use general-purpose wildcards in SDC generator
2020-06-11 19:31:02 -06:00
e811f8bb21
plug in netlist manager and now the include_netlist appears in one unique file
2020-04-23 20:42:11 -06:00
87b17fc25f
add netlist manager data structure
2020-04-23 18:59:09 -06:00
68b7991a46
bug fixed for sdc on memory blocks
2020-04-21 13:37:56 -06:00
d325bede68
add fabric bitstream writer
2020-04-21 12:02:10 -06:00
e10cafe0a5
Critical patch on repacking about wire LUT support.
...
Previously, the wire LUT identification is too naive and does not consider all the cases
2020-04-19 16:42:31 -06:00
b9dab2baaf
add exit codes to command execution in shell context
2020-04-08 16:18:05 -06:00
1fb37f4c71
improve directory creator to support same functionality as 'mkdir -p'
2020-04-08 12:55:09 -06:00
cbcd1d20d4
fixed memory leakage in pb_pin fixup
2020-04-07 16:24:04 -06:00
5a04da2082
fix memory leakage in openfpga title
2020-04-07 16:14:41 -06:00
bcb86801fa
bug fixed in gpio naming for module manager ports
2020-04-05 17:26:44 -06:00
e601a648cc
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
2020-03-27 19:07:34 -06:00
7c9c2451f2
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
2020-03-27 16:03:42 -06:00
329b0a9cf1
add options to enable SDC constraints on zero-delay paths
2020-03-25 15:55:30 -06:00
c2e5d6b8e2
add options to dsiable SDC for non-clock global ports
2020-03-25 14:38:13 -06:00
787dc8ce83
added ASCII OpenFPGA logo in shell interface
2020-03-25 11:16:04 -06:00
9e4e12aae9
fixed echo message in the compression rate of gsb uniquifying
2020-03-22 16:13:04 -06:00
ff474d87de
fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
2020-03-22 16:11:00 -06:00
3958ac2494
fix bugs in flow manager on default compress routing problems
2020-03-22 15:26:15 -06:00
7b9384f3b2
add write_gsb command to shell interface
2020-03-21 19:40:26 -06:00
9a518e8bb6
bug fixed for tileable rr_graph builder for more 4x4 fabrics
2020-03-21 18:07:00 -06:00
c0e8d98c6f
bug fixed in tile direct builder
2020-03-21 12:43:56 -06:00
aff73bdd74
deployed edge sorting and make it as an option to link_arch command
2020-03-08 15:59:53 -06:00
37423729ec
bug fixing for naming the duplicated pins
2020-03-07 15:44:57 -07:00
7fcd27e000
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
2020-03-03 12:29:58 -07:00
3241d8bd37
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
2020-03-02 19:54:18 -07:00
037c7e5c43
adapt top-level function for analysis SDC writer
2020-03-02 17:58:44 -07:00
a17c14c363
clean-up command addition and add fabric bitstream building to sample script
2020-03-02 10:39:19 -07:00
aa66042dfb
move simulation setting annotation to a separated source file
2020-02-29 15:19:02 -07:00
7b18f7cd09
now the auto select number of clocks in simulation is online
2020-02-29 13:29:16 -07:00
542fadaaae
allow users to use VPR critical path delay in OpenFPGA simulation
2020-02-28 12:10:27 -07:00
de8425874c
use user defined critical path delay in SDC generation
2020-02-28 11:24:39 -07:00
092e10afda
bring pnr sdc generator online and fixed minor bugs in bitstream writing
2020-02-28 11:14:50 -07:00
9b769cd8e4
bug fix for using renamed i/o names
2020-02-27 16:37:20 -07:00
078f72320f
debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
2020-02-27 13:24:26 -07:00
f558405887
ported verilog testbench generator online. Split from fabric generator. Testing to be done
2020-02-27 12:33:09 -07:00
b3796b0818
build io location map
2020-02-26 19:58:18 -07:00
25e0583636
add io location map data structure and start porting verilog testbench generator
2020-02-26 17:10:57 -07:00
a26d31b87f
make write bitstream online
2020-02-26 11:09:23 -07:00
4024ed63cb
add truth table build up for physical LUTs
2020-02-25 22:39:42 -07:00
tangxifan