tangxifan
|
ee0459d729
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[core] developing append_clock_rr_graph function
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2023-02-24 17:58:37 -08:00 |
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tangxifan
|
aa55c692d7
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[core] starting developing core function for clock rr_graph build-up
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2023-02-23 18:04:07 -08:00 |
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tangxifan
|
786b458a27
|
[core] adding new command 'append_clock_rr_graph'
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2023-02-23 13:30:18 -08:00 |
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tangxifan
|
b78ca69fe5
|
[core] enable clock arch link
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2023-02-22 22:29:16 -08:00 |
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tangxifan
|
e1dab3d227
|
[code] format
|
2023-02-22 22:01:24 -08:00 |
|
tangxifan
|
e175472a07
|
[core] adding new commands
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2023-02-22 21:58:25 -08:00 |
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tangxifan
|
f00acf1e62
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[code] fixed all the compiler warnings under openfpga/src
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2023-01-31 12:51:52 -08:00 |
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tangxifan
|
c55d54d325
|
[code] format
|
2023-01-11 17:19:04 -08:00 |
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tangxifan
|
c00c43cbd4
|
[core] fixed a few bugs
|
2023-01-11 16:39:25 -08:00 |
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tangxifan
|
9bbb09ef0f
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[core] adding a new command 'exec_external' to run system call
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2023-01-11 16:31:26 -08:00 |
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tangxifan
|
b569d6b603
|
[core] format
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2023-01-07 11:40:17 -08:00 |
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tangxifan
|
c7a4d25e35
|
[core] now all the commands can be optionally hidden
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2023-01-07 11:36:10 -08:00 |
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tangxifan
|
4385b364af
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[code] now setup command can be hidden optionally
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2023-01-07 11:18:43 -08:00 |
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tangxifan
|
52e803804d
|
[core] add missing file
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2023-01-06 22:37:55 -08:00 |
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tangxifan
|
2fc047daff
|
[core] format
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2023-01-06 21:11:12 -08:00 |
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tangxifan
|
cf824e7161
|
[core] now bitstream commands follow templates
|
2023-01-06 21:08:50 -08:00 |
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tangxifan
|
26c294679a
|
[core] now setup commands follow templates
|
2023-01-06 20:52:37 -08:00 |
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tangxifan
|
a99794f51c
|
[core] now FPGA-SDC commands follow templates
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2023-01-06 19:22:51 -08:00 |
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tangxifan
|
401b640852
|
[core] format
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2023-01-06 17:50:47 -08:00 |
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tangxifan
|
12134f4106
|
[core] now openfpga verilog commands follow templates
|
2023-01-06 17:48:00 -08:00 |
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tangxifan
|
93c00207ab
|
[core] now command functions are templates, which can be used by other extensions
|
2023-01-06 17:23:01 -08:00 |
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tangxifan
|
5606566839
|
[engine] format
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2023-01-01 17:37:44 -08:00 |
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tangxifan
|
7610e536bf
|
[engine] now 'source' command can be seen in help desk
|
2023-01-01 12:01:37 -08:00 |
|
tangxifan
|
76570e653c
|
[engine] format
|
2023-01-01 10:23:18 -08:00 |
|
tangxifan
|
c90f8389f1
|
[engine] debugged
|
2023-01-01 10:22:47 -08:00 |
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tangxifan
|
8d947c7bdb
|
[engine] now developers can write their superset command based on other commands through openfpga shell
|
2023-01-01 10:10:09 -08:00 |
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tangxifan
|
f1a317b384
|
[engine] format
|
2022-11-24 21:04:04 -08:00 |
|
tangxifan
|
24a174c7a4
|
[engine] fixed syntax errors
|
2022-11-23 17:06:27 -08:00 |
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tangxifan
|
07424b1e7f
|
[engine] now main() is encapuslated in a class OpenfpgaShell
|
2022-11-23 16:52:22 -08:00 |
|
tangxifan
|
c4de6655b6
|
[engine] bug
|
2022-10-17 15:26:21 -07:00 |
|
tangxifan
|
0f2b8da7f0
|
[engine] code format
|
2022-10-17 14:55:34 -07:00 |
|
tangxifan
|
63d8b00630
|
[engine] syntax
|
2022-10-17 14:54:18 -07:00 |
|
tangxifan
|
11624cd0c6
|
[engine] enabling new feature: pin_table_direction_convention
|
2022-10-17 14:08:21 -07:00 |
|
tangxifan
|
6d31b319a2
|
[engine] update source files subject to code formatting rules
|
2022-10-06 17:08:50 -07:00 |
|
tangxifan
|
fb2693171b
|
[engine] fixed a bug which causes errors in repacker
|
2022-09-28 16:30:11 -07:00 |
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tangxifan
|
36b3e64b35
|
[engine] now pb_fixup can also accept vtr's post-routing-clustering sync up results
|
2022-09-28 12:17:16 -07:00 |
|
tangxifan
|
3285af4107
|
[engine] syntax
|
2022-09-28 11:39:37 -07:00 |
|
tangxifan
|
51f54bbf20
|
[engine] developing the steps to annotate clustering results
|
2022-09-27 16:54:48 -07:00 |
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tangxifan
|
3c6ef1925c
|
[engine] now sort ipin incoming edges
|
2022-09-19 11:00:08 -07:00 |
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tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
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tangxifan
|
2fc124e109
|
[engine] now repack has a new option "--ignore_global_nets_on_pins"
|
2022-09-12 16:18:26 -07:00 |
|
tangxifan
|
56619f9a47
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-07 15:04:05 -07:00 |
|
tangxifan
|
eab3580f79
|
[engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity
|
2022-09-06 13:40:29 -07:00 |
|
tangxifan
|
71ad0721a1
|
Merge branch 'master' into vtr_upgrade
|
2022-08-31 13:56:17 -07:00 |
|
tangxifan
|
3656154913
|
[engine] fixed syntax errors
|
2022-08-29 21:17:48 -07:00 |
|
tangxifan
|
12a30196e0
|
[engine] updating gsb writer; Unfinished!!!
|
2022-08-29 16:58:48 -07:00 |
|
tangxifan
|
ba6ae05091
|
[engine] update vtr and add in_edge checks to link_arch
|
2022-08-24 12:22:20 -07:00 |
|
tangxifan
|
5d6a90d983
|
[engine] remove compile warnings
|
2022-08-22 20:59:50 -07:00 |
|
tangxifan
|
800ce6a290
|
[engine] avoid function naming conflicts
|
2022-08-18 19:33:56 -07:00 |
|
tangxifan
|
e9c4d102c1
|
[engine] rename files to avoid conflicts with VPR files
|
2022-08-17 20:01:50 -07:00 |