[core] now command functions are templates, which can be used by other extensions
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tangxifan
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e57e5b2d05
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93c00207ab
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@ -1,23 +0,0 @@
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#ifndef OPENFPGA_SPICE_H
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#define OPENFPGA_SPICE_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "command.h"
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#include "command_context.h"
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#include "openfpga_context.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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int write_fabric_spice(OpenfpgaContext& openfpga_ctx, const Command& cmd,
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const CommandContext& cmd_context);
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} /* end namespace openfpga */
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#endif
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@ -1,94 +1,11 @@
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/********************************************************************
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* Add commands to the OpenFPGA shell interface,
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* in purpose of generate SPICE netlists modeling the full FPGA fabric
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* This is one of the core engine of openfpga, including:
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* - generate_fabric_spice : generate Verilog netlists about FPGA fabric
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* - TODO: generate_spice_top_testbench : generate SPICE testbenches for
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*top-level module
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* - TODO: generate_spice_grid_testbench : generate SPICE testbenches for grids
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* - TODO: generate_spice_cb_testbench : generate SPICE testbenches for
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*connection blocks
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* - TODO: generate_spice_sb_testbench : generate SPICE testbenches for switch
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*blocks
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* - TODO: generate_spice_lut_testbench : generate SPICE testbenches for Look-Up
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*Tables
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* - TODO: generate_spice_hard_logic_testbench : generate SPICE testbenches for
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*all the hard logics
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* - TODO: generate_spice_local_routing_testbench : generate SPICE testbenches
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*for local routing
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* - TODO: generate_spice_cb_routing_testbench : generate SPICE testbenches for
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*routing circuit inside connection blocks
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* - TODO: generate_spice_sb_routing_testbench : generate SPICE testbenches for
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*routing circuit inside switch blocks
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*******************************************************************/
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#include "openfpga_spice_command_template.h"
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#include "openfpga_spice_command.h"
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#include "openfpga_spice.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* - Add a command to Shell environment: generate fabric Verilog
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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static ShellCommandId add_openfpga_write_fabric_spice_command(
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openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_fabric_spice");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option(
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"file", true, "Specify the output directory for SPICE netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false,
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"Use explicit port mapping in Verilog netlists");
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* Add command 'write_fabric_spice' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(
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shell_cmd, "generate SPICE netlists modeling full FPGA fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_fabric_spice);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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void add_openfpga_spice_commands(openfpga::Shell<OpenfpgaContext>& shell) {
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/* Get the unique id of 'build_fabric' command which is to be used in creating
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* the dependency graph */
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const ShellCommandId& build_fabric_cmd_id =
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shell.command(std::string("build_fabric"));
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/* Add a new class of commands */
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ShellCommandClassId openfpga_spice_cmd_class =
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shell.add_command_class("FPGA-SPICE");
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/********************************
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* Command 'write_fabric_spice'
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*/
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/* The 'write_fabric_spice' command should NOT be executed before
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* 'build_fabric' */
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std::vector<ShellCommandId> fabric_spice_dependent_cmds;
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fabric_spice_dependent_cmds.push_back(build_fabric_cmd_id);
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add_openfpga_write_fabric_spice_command(shell, openfpga_spice_cmd_class,
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fabric_spice_dependent_cmds);
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/********************************
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* TODO: Command 'write_spice_top_testbench'
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*/
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/* The command 'write_spice_top_testbench' should NOT be executed before
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* 'build_fabric' */
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add_spice_command_templates<OpenfpgaContext>(shell);
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}
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} /* end namespace openfpga */
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@ -0,0 +1,100 @@
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#ifndef OPENFPGA_SPICE_COMMAND_TEMPLATE_H
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#define OPENFPGA_SPICE_COMMAND_TEMPLATE_H
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/********************************************************************
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* Add commands to the OpenFPGA shell interface,
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* in purpose of generate SPICE netlists modeling the full FPGA fabric
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* This is one of the core engine of openfpga, including:
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* - generate_fabric_spice : generate Verilog netlists about FPGA fabric
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* - TODO: generate_spice_top_testbench : generate SPICE testbenches for
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*top-level module
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* - TODO: generate_spice_grid_testbench : generate SPICE testbenches for grids
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* - TODO: generate_spice_cb_testbench : generate SPICE testbenches for
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*connection blocks
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* - TODO: generate_spice_sb_testbench : generate SPICE testbenches for switch
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*blocks
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* - TODO: generate_spice_lut_testbench : generate SPICE testbenches for Look-Up
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*Tables
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* - TODO: generate_spice_hard_logic_testbench : generate SPICE testbenches for
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*all the hard logics
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* - TODO: generate_spice_local_routing_testbench : generate SPICE testbenches
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*for local routing
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* - TODO: generate_spice_cb_routing_testbench : generate SPICE testbenches for
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*routing circuit inside connection blocks
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* - TODO: generate_spice_sb_routing_testbench : generate SPICE testbenches for
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*routing circuit inside switch blocks
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*******************************************************************/
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#include "shell.h"
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#include "openfpga_spice_template.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* - Add a command to Shell environment: generate fabric Verilog
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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template <class T>
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ShellCommandId add_write_fabric_spice_command_template(
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openfpga::Shell<T>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_fabric_spice");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option(
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"file", true, "Specify the output directory for SPICE netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false,
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"Use explicit port mapping in Verilog netlists");
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* Add command 'write_fabric_spice' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(
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shell_cmd, "generate SPICE netlists modeling full FPGA fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_fabric_spice_template<T>);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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template <class T>
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void add_spice_command_templates(openfpga::Shell<T>& shell) {
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/* Get the unique id of 'build_fabric' command which is to be used in creating
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* the dependency graph */
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const ShellCommandId& build_fabric_cmd_id =
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shell.command(std::string("build_fabric"));
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/* Add a new class of commands */
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ShellCommandClassId openfpga_spice_cmd_class =
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shell.add_command_class("FPGA-SPICE");
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/********************************
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* Command 'write_fabric_spice'
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*/
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/* The 'write_fabric_spice' command should NOT be executed before
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* 'build_fabric' */
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std::vector<ShellCommandId> fabric_spice_dependent_cmds;
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fabric_spice_dependent_cmds.push_back(build_fabric_cmd_id);
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add_write_fabric_spice_command_template<T>(shell, openfpga_spice_cmd_class,
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fabric_spice_dependent_cmds);
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/********************************
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* TODO: Command 'write_spice_top_testbench'
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*/
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/* The command 'write_spice_top_testbench' should NOT be executed before
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* 'build_fabric' */
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}
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} /* end namespace openfpga */
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#endif
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@ -1,16 +1,12 @@
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/********************************************************************
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* This file includes functions to compress the hierachy of routing architecture
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*******************************************************************/
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/* Headers from vtrutil library */
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#ifndef OPENFPGA_SPICE_TEMPLATE_H
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#define OPENFPGA_SPICE_TEMPLATE_H
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#include "vtr_log.h"
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#include "vtr_time.h"
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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#include "openfpga_spice.h"
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#include "spice_api.h"
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/* Include global variables of VPR */
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#include "command.h"
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#include "command_context.h"
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#include "globals.h"
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/* begin namespace openfpga */
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@ -19,8 +15,9 @@ namespace openfpga {
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/********************************************************************
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* A wrapper function to call the fabric SPICE generator of FPGA-SPICE
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*******************************************************************/
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int write_fabric_spice(OpenfpgaContext& openfpga_ctx, const Command& cmd,
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const CommandContext& cmd_context) {
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template <class T>
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int write_fabric_spice_template(T& openfpga_ctx, const Command& cmd,
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const CommandContext& cmd_context) {
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CommandOptionId opt_output_dir = cmd.option("file");
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CommandOptionId opt_explicit_port_mapping =
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cmd.option("explicit_port_mapping");
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@ -47,3 +44,5 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx, const Command& cmd,
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}
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} /* end namespace openfpga */
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#endif
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