tangxifan
|
4ea5756be6
|
bug fixed for std cell MUX2 architecture and add the case to regression tests
|
2019-11-06 16:06:47 -07:00 |
|
tangxifan
|
09eb373a6e
|
bug fixing for autocheck top testbench where clock port is not default names
|
2019-11-06 12:21:20 -07:00 |
|
tangxifan
|
00280b835e
|
reorganize regression tests
|
2019-11-05 16:31:42 -07:00 |
|
tangxifan
|
7952d134b9
|
add tree-like mux test case to regression test
|
2019-11-05 16:24:39 -07:00 |
|
tangxifan
|
a308a13d7c
|
use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
|
2019-11-05 15:41:59 -07:00 |
|
tangxifan
|
0ec465d4e1
|
refactoring auto-check top Verilog testbench
|
2019-11-03 17:41:29 -07:00 |
|
tangxifan
|
dc241e6c03
|
add explicit port mapping support in testbenches; remove dangling ports in benchmarks
|
2019-11-02 23:03:47 -06:00 |
Ganesh Gore
|
a880802803
|
Bug Fix: Corrected read VPR stat filename
|
2019-11-01 20:51:05 -06:00 |
|
tangxifan
|
e2b042c61c
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-11-01 18:27:27 -06:00 |
|
Ganesh Gore
|
370a5ed408
|
Bug Fix: shifter ff.v include path to tcl script
|
2019-11-01 18:22:40 -06:00 |
|
Ganesh Gore
|
595d2d3070
|
Simple argument shuffle
|
2019-11-01 18:21:26 -06:00 |
|
Ganesh Gore
|
27005d6640
|
Added Modelsim Python Script
|
2019-11-01 18:20:40 -06:00 |
|
tangxifan
|
49bfb3223c
|
add compact routing to regression test
|
2019-11-01 10:53:47 -06:00 |
|
tangxifan
|
531cc064fc
|
bug fixing for formal top-level testbench
|
2019-11-01 10:47:40 -06:00 |
|
Ganesh Gore
|
da0778e813
|
Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev
|
2019-11-01 00:46:34 -06:00 |
|
tangxifan
|
d709868463
|
adding more regression tests which is quick run but very helpful for debugging
|
2019-10-31 20:17:40 -06:00 |
|
tangxifan
|
a6a3e7c36b
|
adding mcnc_big20 to regression test
|
2019-10-31 19:31:27 -06:00 |
|
Ganesh Gore
|
81180939ca
|
Bug fix: Missing exit_if_fail flag in fpga_flow script
|
2019-10-31 09:56:57 -06:00 |
|
tangxifan
|
5531422186
|
update regression test with no-explicit port mapping cases
|
2019-10-30 19:37:06 -06:00 |
|
tangxifan
|
55fbd72293
|
many bugs have been fixed
|
2019-10-30 15:50:42 -06:00 |
|
tangxifan
|
4398cffaaa
|
single mode is working, multi-mode is under debugging
|
2019-10-29 22:32:36 -06:00 |
|
tangxifan
|
10491c4291
|
bring single mode test case online with bug fixing
|
2019-10-28 17:04:10 -06:00 |
|
tangxifan
|
5cb3717433
|
add single mode test case to regression test. debugging now
|
2019-10-28 15:57:17 -06:00 |
|
Ganesh Gore
|
c034b871bb
|
Made activity file independent of power option
|
2019-10-15 16:08:25 -06:00 |
|
Ganesh Gore
|
eaf8ecee86
|
added _vpr.txt subscript to vpr log files
|
2019-10-15 16:07:34 -06:00 |
Baudouin Chauviere
|
027272c976
|
Faster regression test
|
2019-10-05 12:10:55 -06:00 |
|
Baudouin Chauviere
|
db059af8b8
|
Lighten the regression test
|
2019-10-03 13:33:28 -06:00 |
|
Baudouin Chauviere
|
c7e1f7d90b
|
Added explicit_verilog to regression test in a clean way
|
2019-10-03 10:17:04 -06:00 |
|
Baudouin Chauviere
|
33e50bbc8c
|
fix
|
2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
|
7c3ab38410
|
Hot fix
|
2019-10-01 16:40:16 -06:00 |
|
Ganesh Gore
|
069f628bb0
|
Merge branch 'dev' of github.com:LNIS-Projects/OpenFPGA into ganesh_dev
|
2019-09-28 11:21:37 -06:00 |
|
Ganesh Gore
|
d269472daf
|
Updated formality python script
|
2019-09-27 14:00:57 -06:00 |
AurelienUoU
|
feddcbcb21
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-23 11:41:38 -06:00 |
|
tangxifan
|
5efea159c5
|
Simplify part of regression test to min_route_chan_width
|
2019-09-22 11:14:33 -06:00 |
|
Ganesh Gore
|
1dffe54807
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-22 00:21:25 -06:00 |
|
Ganesh Gore
|
50039a4b6e
|
Added remove run directory option
|
2019-09-21 23:35:56 -06:00 |
|
AurelienUoU
|
cc0bfdd548
|
Add testcase in regression test for architecture with 1 IO cell/IO block
|
2019-09-20 10:27:26 -06:00 |
|
tangxifan
|
4e7af5cdc5
|
update tileable_routing test
|
2019-09-18 15:59:32 -06:00 |
|
tangxifan
|
0f0d06aad7
|
add non-LUT intermediate buffer to test and apply minor bug fix
|
2019-09-18 15:04:51 -06:00 |
|
Ganesh Gore
|
8afcba2c45
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-18 12:15:42 -06:00 |
|
Ganesh Gore
|
cd5fd6ce6c
|
Added explicit checking to VVP execution
|
2019-09-18 12:14:26 -06:00 |
|
Ganesh Gore
|
56c40ca06d
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-17 22:12:11 -06:00 |
|
Ganesh Gore
|
169732ccc1
|
Added verbose option in VVP output
|
2019-09-17 22:09:37 -06:00 |
|
tangxifan
|
d7ac7d3649
|
start refactoring the switch block verilog generation
|
2019-09-17 20:40:26 -06:00 |
|
Ganesh Gore
|
7be83235a0
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-16 21:25:26 -06:00 |
|
Ganesh Gore
|
678e3181ba
|
Made compact_routing_hierarchy options uncond
|
2019-09-16 21:22:13 -06:00 |
|
tangxifan
|
5abbfd6a0f
|
add tileable routing to regression test
|
2019-09-16 20:45:02 -06:00 |
|
Ganesh Gore
|
81b9c5b266
|
Added flag for VVP exit code
|
2019-09-14 12:35:47 -06:00 |
|
Ganesh Gore
|
d90329678a
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-09-14 12:11:36 -06:00 |
|
Ganesh Gore
|
ec3854a648
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-14 00:14:17 -06:00 |
|
Ganesh Gore
|
e5c99c8b12
|
Quick terminate on fail added
|
2019-09-13 23:56:38 -06:00 |
|
Ganesh Gore
|
bd9e57bc37
|
Added better task name
|
2019-09-13 23:30:42 -06:00 |
|
Ganesh Gore
|
a6e592247e
|
Replaced options exit_on fail and show_thread logs
|
2019-09-13 22:50:20 -06:00 |
|
Ganesh Gore
|
d64bb18346
|
Separated Modelsim tcl script generation
|
2019-09-07 12:36:22 -04:00 |
|
Ganesh Gore
|
d55b7e9497
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-06 11:49:38 -04:00 |
|
Ganesh Gore
|
bcbcd463fe
|
Added pending runs in log
|
2019-09-06 11:48:13 -04:00 |
|
Ganesh Gore
|
9abc1e1e7d
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-05 13:12:41 -04:00 |
|
Ganesh Gore
|
702a7683a8
|
Ensure strict exit of fpga_flow on error
|
2019-09-05 10:23:35 -06:00 |
|
tangxifan
|
d2d750a15c
|
debugged rram mux branch Verilog generation
|
2019-09-02 16:21:29 -06:00 |
|
Ganesh Gore
|
48ec1eefcd
|
Added fpga_task cmd options in doc [ci skip]
|
2019-09-02 02:45:05 -06:00 |
|
Ganesh Gore
|
e37ac1a565
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-02 00:19:19 -06:00 |
|
Ganesh Gore
|
241b001282
|
Added openfpga_task doc
|
2019-09-01 22:15:53 -06:00 |
|
Ganesh Gore
|
ad4c688206
|
Added print for JobID to architecture mapping
|
2019-08-31 22:04:57 -06:00 |
|
Ganesh Gore
|
f4e99c150a
|
resolve missing variable bug
|
2019-08-31 21:55:32 -06:00 |
|
Ganesh Gore
|
3d4f7f66fd
|
Updated to run with python3
|
2019-08-31 21:42:31 -06:00 |
|
Ganesh Gore
|
06c0dbb328
|
Added docuementation for fpga_flow
|
2019-08-31 15:19:34 -06:00 |
|
Ganesh Gore
|
02137805c7
|
Added python version check in flow and task scripts
|
2019-08-29 22:14:30 -06:00 |
|
Ganesh Gore
|
a25124b58c
|
Added additional PATH variables
|
2019-08-29 21:37:07 -06:00 |
|
Ganesh Gore
|
f54a8522fa
|
Log prints task stats
|
2019-08-27 22:04:32 -06:00 |
|
Ganesh Gore
|
903c2b7705
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-27 21:38:17 -06:00 |
|
Ganesh Gore
|
715adc13ff
|
Failed result do not throw error
|
2019-08-27 21:25:38 -06:00 |
|
tangxifan
|
94538b5062
|
add more testing architecture
|
2019-08-27 18:44:58 -06:00 |
|
tangxifan
|
f04565386f
|
refactored behavioral mux branch verilog generation
|
2019-08-27 18:39:25 -06:00 |
|
tangxifan
|
de8a6bc833
|
update regression tests
|
2019-08-26 21:00:15 -06:00 |
|
Ganesh Gore
|
7a3ff94116
|
Added blif task in travis script
|
2019-08-25 01:28:21 -06:00 |
|
Ganesh Gore
|
937ebd1b85
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-08-25 00:53:18 -06:00 |
|
Ganesh Gore
|
632c9d6976
|
Added python execution path in config file
|
2019-08-25 00:42:48 -06:00 |
|
Ganesh Gore
|
f558437ae1
|
Added task for vpr_blif flow
|
2019-08-25 00:23:39 -06:00 |
|
tangxifan
|
3fb3082447
|
add more tests
|
2019-08-23 14:10:01 -06:00 |
|
Ganesh Gore
|
52d6a9e979
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-23 13:41:29 -06:00 |
|
Ganesh Gore
|
28dde899db
|
Updated Architecture Template
|
2019-08-23 12:44:45 -06:00 |
|
tangxifan
|
520630c5e2
|
add more testing tasks
|
2019-08-23 10:16:52 -06:00 |
|
Ganesh Gore
|
6e7de16ad4
|
Solved bug in commnad rearrangement
|
2019-08-22 23:41:25 -06:00 |
|
Ganesh Gore
|
89589ddc1c
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-08-22 18:46:51 -06:00 |
|
Ganesh Gore
|
77e2a7bca3
|
Added execution time logs in flow script
|
2019-08-22 17:01:38 -06:00 |
|
Ganesh Gore
|
30cbe38d3d
|
Added Test Modes - Added blif VPR Option
|
2019-08-22 17:00:59 -06:00 |
|
Ganesh Gore
|
d5ce1b557e
|
Made thread logs prettier
|
2019-08-22 16:56:58 -06:00 |
|
Ganesh Gore
|
764d7039b5
|
Import utils bug fixing for travis test
|
2019-08-21 12:42:58 -06:00 |
|
Ganesh Gore
|
2f0acfad23
|
Updated travis to run regression task
|
2019-08-21 11:09:53 -06:00 |
|
Ganesh Gore
|
e51ff44710
|
Added execution time information in logs
|
2019-08-21 11:08:47 -06:00 |
|
Ganesh Gore
|
a335a57c6c
|
Added debug option to commnad line arguments
|
2019-08-21 11:08:13 -06:00 |
|
tangxifan
|
59f1ac7310
|
add missing files and try to refactor submodule essential
|
2019-08-20 20:49:26 -06:00 |
|
tangxifan
|
5f55fc7b49
|
add missing files and developing essential gates
|
2019-08-20 20:43:46 -06:00 |
|
tangxifan
|
60e8d2b29f
|
add missing files and try to refactor submodule essential
|
2019-08-20 16:13:08 -06:00 |
|
Ganesh Gore
|
b7484ef178
|
Removed traces of old template file
|
2019-08-20 15:58:19 -06:00 |
|
Ganesh Gore
|
afee2229af
|
Removed unused templates and file from openfpga_flow directory
|
2019-08-19 21:32:52 -06:00 |
|
Ganesh Gore
|
08b0ef3550
|
Updated validate_command_line_arguments function
+ Checks if valid flow is provided as a argument
+ Command line argument list validated with dependencies provided in configuration file
|
2019-08-19 21:28:23 -06:00 |
|
Ganesh Gore
|
53941eaf5c
|
Changed yosys output file name
|
2019-08-19 19:06:46 -06:00 |
|
Ganesh Gore
|
8d0153d34e
|
Added gitignore to skip run directory tracking
|
2019-08-19 19:06:01 -06:00 |
|
Ganesh Gore
|
616d7706c9
|
Added list of intermidiate files filename
|
2019-08-19 19:05:08 -06:00 |