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320 Commits

Author SHA1 Message Date
tangxifan 150653287d [core] supporting io naming for verilog testbench generators 2023-06-25 15:29:27 -07:00
tangxifan bdda695cc0 [core] format 2023-06-18 21:18:35 -07:00
tangxifan cef573529d [core] now fpga verilog can output fpga core netlist 2023-06-18 21:17:50 -07:00
tangxifan b6c90eb99a [core] fixed several bugs which causes bgf and pcf support in mock wrapper failed 2023-05-27 12:13:16 -07:00
tangxifan e1feebc96d [core] fixing bugs on pcf and bgf support for mock efpga wrapper 2023-05-26 21:54:08 -07:00
tangxifan 0abc5af1a9 [core] fixed the bug supporting global nets 2023-05-26 20:44:04 -07:00
tangxifan a9e5e1af89 [core] now fabric netlist include mock wrapper 2023-05-26 18:49:57 -07:00
tangxifan 788b1495dd [core] split a big function to 4 sub functions so that we can efficiently reuse for mock wrapper 2023-05-26 17:31:07 -07:00
tangxifan f7afbfa0bd [core] fixed some bugs 2023-05-26 12:26:30 -07:00
tangxifan e9848c5728 [core] typo 2023-05-26 10:24:21 -07:00
tangxifan 45e25e4152 [core] hooking up API with command 2023-05-25 19:50:39 -07:00
tangxifan affe5c5d1e [core] developing mock wrapper generator 2023-05-25 18:50:47 -07:00
tangxifan e11e4dc3f4 [core] comment on current limitations 2023-04-24 14:59:43 +08:00
tangxifan d9af8dd722 [core] did some dirty fix but now dv should pass. Not sure why usig a shorter bitstream does not work 2023-04-24 14:50:42 +08:00
tangxifan 679c6e9b43 [core] debugging 2023-04-24 14:05:51 +08:00
tangxifan 3c6a4d34d8 [core] code format 2023-04-24 13:36:59 +08:00
tangxifan 715765d81b [core] code complete for top testbench generator on ccffv2 upgrades 2023-04-24 13:34:44 +08:00
tangxifan 667d9df028 [core] developing testbench generator for ccff v2 2023-04-24 11:36:21 +08:00
tangxifan f00acf1e62 [code] fixed all the compiler warnings under openfpga/src 2023-01-31 12:51:52 -08:00
tangxifan e2debd2dde [engine] add missing header files after coding formatter sorts the include files 2022-10-06 18:08:57 -07:00
tangxifan 6d31b319a2 [engine] update source files subject to code formatting rules 2022-10-06 17:08:50 -07:00
tangxifan dfe30df462 [engine] resolve compilation warnings 2022-08-17 16:32:21 -07:00
tangxifan e0ae851e28 [engine] correcting compilation errors due to vpr upgrade 2022-08-17 16:25:12 -07:00
tangxifan 8ab090651a [FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports 2022-03-16 20:51:37 +08:00
tangxifan 235887e03a [FPGA-Verilog] Fixed a bug on config-enable signals 2022-02-23 22:35:23 -08:00
tangxifan 086642d134 [FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly 2022-02-23 15:33:24 -08:00
tangxifan 1c18d14ad5 [FPGA-Verilog] Add big/little endian support to output ports 2022-02-19 09:23:48 -08:00
tangxifan 3e43a60fdc [FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks 2022-02-19 09:15:38 -08:00
tangxifan 671188dfa4 [FPGA-Verilog] Now support big/little-endian in bus group 2022-02-18 23:05:03 -08:00
tangxifan 790715f46a [FPGA-Verilog] Fixing bugs when using bus group in full testbench generator 2022-02-18 15:41:35 -08:00
tangxifan 401f673f16 [FPGA-Verilog] Streamline codes by using APIs 2022-02-18 14:47:36 -08:00
tangxifan c16ea8d082 [FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches 2022-02-18 14:34:32 -08:00
tangxifan a4dc86a33d [FPGA-Verilog] Now output atom block name removal has a dedicated function 2022-02-18 14:30:46 -08:00
tangxifan f5dd89bbd9 [FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used 2022-02-18 14:08:03 -08:00
tangxifan 0d620888ab [FPGA-Verilog] Now instance can output bus ports with all the pins 2022-02-18 12:03:26 -08:00
tangxifan aa375fd7a4 [FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator 2022-02-18 11:31:11 -08:00
tangxifan 6da0ede9b0 [FPGA-Verilog] Adding bus group support to all Verilog testbench generators 2022-02-17 23:48:44 -08:00
tangxifan c96f0d199d [FPGA-Verilog] Adding bus group support in Verilog testbenches 2022-02-17 23:14:28 -08:00
tangxifan e67f8ad8b2 [FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase 2022-02-15 17:19:50 -08:00
tangxifan be8f18310d [FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances 2022-02-14 17:16:26 -08:00
tangxifan d3f68db228 [FPGA-Verilog] fixing bugs in reset ports for counters in full testbenches 2022-02-14 17:00:54 -08:00
tangxifan 34e192c5ca [FPGA-Verilog] Fixed a bug on wiring FPGA global ports 2022-02-14 15:21:29 -08:00
tangxifan 8d48492ec0 [FPGA-Verilog] Add clock ports to the white list when adding postfix 2022-02-14 11:09:00 -08:00
tangxifan 5794561f7b [FPGA-Verilog] Now shared input wire/register has a postfix in full testbench 2022-02-14 10:39:27 -08:00
tangxifan 2ca73d79e4 [FPGA-Verilog] Fixed the bug on pin constraints 2022-02-13 22:08:06 -08:00
tangxifan b1377f0d34 [FPGA-Verilog] Fix syntax errors 2022-02-13 20:29:05 -08:00
tangxifan 6e132aace4 [FPGA-Verilog] Remove the prefix added by VPR in preconfigured top module 2022-02-13 20:26:21 -08:00
tangxifan fb4106de19 [FPGA-Verilog] Fixed a bug in naming mismatch 2022-02-13 20:06:35 -08:00
tangxifan a068237082 [FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks 2022-02-13 19:55:16 -08:00
tangxifan 1c94d0f285 [FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path`` 2022-02-01 13:25:09 -08:00
tangxifan f311a034bb [FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path`` 2022-02-01 12:17:02 -08:00
tangxifan 2b8e2de0c9 [FPGA-Verilog] Fix bugs 2022-01-31 14:23:04 -08:00
tangxifan 6c29c286bc [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
tangxifan 63f44adf15 [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
Emin Cetin 6c2c4e8b14 adding comment 2022-01-28 08:57:45 +03:00
Emin Cetin f9b47c3b34 missing semicolon 2022-01-27 16:49:04 +03:00
Emin Cetin 8f7ee4e338 changing condition of bitstream downloading 2022-01-27 11:49:55 +03:00
tangxifan 62b57b05d2 [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
tangxifan ff264c00a2 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-31 11:51:34 -07:00
tangxifan 91627abe12 [FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided 2021-10-30 11:53:46 -07:00
tangxifan 546350ae41 [FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks 2021-10-10 23:19:39 -07:00
tangxifan 202b50c0e3 [FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why 2021-10-10 20:57:23 -07:00
tangxifan de3275e9ba [FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains 2021-10-10 16:56:07 -07:00
tangxifan 6aa4991314 [FPGA-Verilog] Bug fix 2021-10-09 21:34:07 -07:00
tangxifan 34575f7222 [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
tangxifan 19a551e641 [Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region 2021-10-09 16:44:04 -07:00
tangxifan 8f5f30792f [Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface 2021-10-08 15:25:37 -07:00
tangxifan 54a8809b3c [FPGA-Verilog] Bug fix in computing clock frequency for shift register chains 2021-10-06 16:49:28 -07:00
tangxifan 27153bbc89 [FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition 2021-10-06 13:38:51 -07:00
tangxifan bf473f50f8 [FPGA-Verilog] Correct bugs in logging clock frequencies 2021-10-06 11:55:57 -07:00
tangxifan fcb5470baa [Lib] Add validator to check if a clock is constrained in simulation settings 2021-10-06 11:48:23 -07:00
tangxifan 82ed6b177b [FPGA-Verilog] Now consider clock constraints for BL/WL shift registers 2021-10-06 11:39:28 -07:00
tangxifan 2badcb58f2 [FPGA-Verilog] Fixed a critical bug in verilog testbench generator for QL memory bank using BL/WL register which causes misalignment in shift register loading 2021-10-03 16:04:47 -07:00
tangxifan 756b4c7dc8 [FPGA-Verilog] Bug fix in estimating the simulation period for QuickLogic memory bank using BL/WL shift registers 2021-10-03 12:11:20 -07:00
tangxifan 3eb601531a [FPGA-Verilog] Many bug fixes 2021-10-02 23:39:53 -07:00
tangxifan d453e6477d [FPGA-Verilog] Bug fix 2021-10-02 22:32:57 -07:00
tangxifan 02af633acd [FPGA-Verilog] Fixed several bugs in testbench generator which caused iVerilog errors 2021-10-02 22:14:15 -07:00
tangxifan fa7e168137 [FPGA-Verilog] Now testbench generator connects global shift register clocks to FPGA ports 2021-10-02 22:08:14 -07:00
tangxifan 76d58ebaa0 [FPGA-Verilog] Move clock generator to generic stimuli and shift register clock period is auto tuned by programming clock period 2021-10-02 21:48:10 -07:00
tangxifan 54ec74d8d2 [FPGA-Verilog] Bug fix in code generator 2021-10-02 17:31:37 -07:00
tangxifan 32fc0a1692 [FPGA-Verilog] Upgrading verilog testbench generator for QuickLogic memory bank using BL/WL shift register 2021-10-02 17:25:27 -07:00
tangxifan 9e5debabe1 [FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks 2021-10-01 16:23:38 -07:00
tangxifan 2bd2788e77 [Engine] Upgrading testbench generator to support QuickLogic memory bank with shift registers 2021-10-01 11:23:40 -07:00
tangxifan 7b010ba0f4 [Engine] Support programming shift register clock in XML syntax 2021-10-01 11:00:38 -07:00
tangxifan 2d4c200d58 [FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists 2021-09-29 20:56:02 -07:00
tangxifan 29c351f5a4 [Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator 2021-09-25 19:34:21 -07:00
tangxifan a56d1f4fdb [FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs 2021-09-25 17:49:15 -07:00
tangxifan c84c0d4a3f [FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR 2021-09-20 17:07:26 -07:00
tangxifan b787c4e100 [Engine] Register QL memory bank as a legal protocol 2021-09-09 15:06:51 -07:00
tangxifan 1aac3197eb [FPGA-Verilog] Upgrade testbench generator to support QL memory bank 2021-09-05 21:38:00 -07:00
tangxifan e9d29e27e5 [Tool] Bug fix 2021-07-02 15:32:30 -06:00
tangxifan 6e6c3e9fa4 [Tool] Patch the critical bug in the use of signal polarity in pin constraints 2021-07-02 15:26:21 -06:00
tangxifan 9074bffa68 [Tool] Support customized default value in pin constraint file 2021-07-01 23:43:19 -06:00
tangxifan d0e4f8521f [Tool] Bug fix on the reset stimuli 2021-07-01 19:58:54 -06:00
tangxifan b5df1f9aeb [Tool] Bug fix for redundant endif in netlists 2021-06-29 17:02:16 -06:00
tangxifan b83eef47b4 [Tool] Bug fix for testbench generation without self checking codes 2021-06-29 16:27:29 -06:00
tangxifan 6a260cadbf [Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose 2021-06-29 15:42:23 -06:00
tangxifan 7ac7de789e [Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes 2021-06-29 15:26:40 -06:00
tangxifan 77dddaeb39 [Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions 2021-06-29 14:26:33 -06:00
tangxifan a3208b332b [Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL 2021-06-29 11:50:53 -06:00