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[core] fixed some bugs

This commit is contained in:
tangxifan 2023-05-26 12:26:30 -07:00
parent e9848c5728
commit f7afbfa0bd
1 changed files with 1 additions and 3 deletions
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4
openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp
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@ -317,8 +317,6 @@ int print_verilog_mock_fpga_wrapper(
circuit_name;
print_verilog_file_header(fp, title, options.time_stamp());
print_verilog_default_net_type_declaration(fp, options.default_net_type());
/* Find the top_module */
ModuleId top_module =
module_manager.find_module(generate_fpga_top_module_name());
@ -335,7 +333,7 @@ int print_verilog_mock_fpga_wrapper(
/* Instanciate application HDL module */
print_verilog_testbench_benchmark_instance(
fp, circuit_name, std::string(APP_INSTANCE_NAME), std::string(),
std::string(), std::string(), std::string(APPINST_PORT_POSTFIX),
std::string(), std::string(APPINST_PORT_POSTFIX), std::string(APPINST_PORT_POSTFIX),
benchmark_clock_port_names, atom_ctx, netlist_annotation, pin_constraints,
bus_group, options.explicit_port_mapping());