tangxifan
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0a7915aa77
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[core] typo
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2024-03-29 12:03:23 -07:00 |
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tangxifan
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6a5d3c7cdc
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[code] syntax
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2024-03-29 11:03:48 -07:00 |
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tangxifan
|
00de794967
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[core] code format
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2024-03-29 10:58:48 -07:00 |
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tangxifan
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981828c39c
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[core] add a new opton ``--dump_waveform`` to command ``write_preconfigured_fabric_wrapper``
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2024-03-29 10:57:45 -07:00 |
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tangxifan
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bacd845139
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[core] code format
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2023-12-08 13:41:41 -08:00 |
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tangxifan
|
5e181cbe72
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[core] add a new option for simulator type to verilog full testbench generator
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2023-12-08 13:07:25 -08:00 |
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tangxifan
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0e945d6e71
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[core] fix a bug in ql memory bank tb where VCS failed
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2023-12-08 11:36:54 -08:00 |
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tangxifan
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b780f0a552
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[core] code format
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2023-11-03 14:39:49 -07:00 |
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tangxifan
|
e48de682ed
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[core] fixed som ebugs
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2023-11-03 14:39:28 -07:00 |
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tangxifan
|
b2e1eb30c7
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[core] code format
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2023-11-03 13:50:04 -07:00 |
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tangxifan
|
21813eb59f
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[core] now full testbench uses bitstream in different sizes
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2023-11-03 13:48:21 -07:00 |
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tangxifan
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2cd3453629
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[core] fixed the bug in ccff v2 on config enable signal drivers
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2023-11-03 10:25:12 -07:00 |
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tangxifan
|
8bee65853c
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[core] add missing files
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2023-11-02 19:01:25 -07:00 |
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tangxifan
|
649d44b2d8
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[core] code format
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2023-11-02 16:33:55 -07:00 |
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tangxifan
|
36fa020c15
|
[core] syntax
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2023-11-02 16:33:19 -07:00 |
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tangxifan
|
75e9e98e5d
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[core] add two new commands to output testbench parts
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2023-11-02 16:06:48 -07:00 |
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tangxifan
|
5bae2bf54d
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[core] code format
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2023-10-19 23:05:49 -07:00 |
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tangxifan
|
4b00651a46
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[core] now name indexing is applied to netlist names
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2023-10-19 23:03:48 -07:00 |
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tangxifan
|
4d11f73471
|
[core] fixed a bug
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2023-09-18 20:43:15 -07:00 |
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tangxifan
|
a1e609c901
|
[core] fixed some bugs
|
2023-09-18 16:39:07 -07:00 |
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tangxifan
|
c6175aa514
|
[core] code format
|
2023-09-17 22:37:48 -07:00 |
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tangxifan
|
ef97127c63
|
[core] fixed some bugs in testbenches when renaming top modules
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2023-09-17 22:34:00 -07:00 |
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tangxifan
|
4ccb4737be
|
[core] code format
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2023-09-17 17:33:10 -07:00 |
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tangxifan
|
f79da76656
|
[core] supporting renaming on all the verilog modules
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2023-09-17 17:29:11 -07:00 |
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tangxifan
|
058bb1ef51
|
[core] code format
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2023-09-16 18:24:38 -07:00 |
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tangxifan
|
6fc2924438
|
[core] syntax
|
2023-09-16 18:16:30 -07:00 |
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tangxifan
|
d61d88f12e
|
[core] fixed some bugs in verilog writer due to renaming
|
2023-09-16 18:13:22 -07:00 |
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tangxifan
|
eaadff3448
|
[core] fixed some bugs
|
2023-09-06 22:49:56 -07:00 |
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tangxifan
|
bcb82d43af
|
[core] code format
|
2023-09-06 22:40:59 -07:00 |
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tangxifan
|
2fee56548b
|
[core] fixed some bugs
|
2023-09-06 22:39:59 -07:00 |
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tangxifan
|
f544953085
|
[core] code format
|
2023-09-06 22:29:30 -07:00 |
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tangxifan
|
f8b2eec988
|
[core] now default net type wire will not appear. timescale does not show in fabric netlists
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2023-09-06 22:27:51 -07:00 |
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tangxifan
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539bcba851
|
[core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types
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2023-09-06 17:23:41 -07:00 |
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tangxifan
|
717906ea17
|
[core] code format
|
2023-08-25 15:13:39 -07:00 |
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tangxifan
|
89b392a51f
|
[core] adapt changes in is_sb_exist()
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2023-08-25 15:13:00 -07:00 |
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tangxifan
|
a6d43beaca
|
[core] now tile verilog writer supports relative paths
|
2023-08-21 22:25:52 -07:00 |
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tangxifan
|
bb945b2816
|
Merge branch 'master' into openfpga-issue-1256
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2023-08-07 13:49:19 -07:00 |
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tangxifan
|
beee2369c9
|
[core] fixed a bug
|
2023-08-05 22:06:17 -07:00 |
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tangxifan
|
64c0839e30
|
[core] now verilog writer supports memory group modules
|
2023-08-04 16:11:33 -07:00 |
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tangxifan
|
a0f81a5bf2
|
[core] now verilog generator can output feedthrough memory module to files
|
2023-08-04 13:34:38 -07:00 |
cschai
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aae037bf77
|
Address comment
|
2023-07-30 02:18:48 -07:00 |
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cschai
|
63459218e5
|
Address comment
|
2023-07-30 00:24:40 -07:00 |
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tangxifan
|
19ed9ea669
|
Merge branch 'master' into openfpga-issue-1256
|
2023-07-26 10:32:30 -07:00 |
|
Chung Shien Chai
|
39934f9d16
|
Address issue 1256
|
2023-07-20 22:34:18 -07:00 |
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tangxifan
|
6607bb7e48
|
[core] now fpga verilog supports tile modules
|
2023-07-18 22:35:22 -07:00 |
|
tangxifan
|
ddfb0c4afd
|
[core] now mock fpga top supports fpga core wrapper
|
2023-06-26 15:06:11 -07:00 |
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tangxifan
|
83fa6a421e
|
[core] code format
|
2023-06-26 10:06:17 -07:00 |
|
tangxifan
|
70f40cd21a
|
[core] fixing bugs in the preconfig module when supporting dut module of fpga_core
|
2023-06-26 10:03:19 -07:00 |
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tangxifan
|
919d6d8608
|
[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
|
2023-06-25 22:49:51 -07:00 |
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tangxifan
|
205881d0e7
|
[core] fixed the bug when using fpga_core instead of fpga_top
|
2023-06-25 18:03:15 -07:00 |