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[core] fixed the bug when using fpga_core instead of fpga_top

This commit is contained in:
tangxifan 2023-06-25 18:03:15 -07:00
parent 150653287d
commit 205881d0e7
2 changed files with 11 additions and 2 deletions
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10
openfpga/src/base/openfpga_verilog_template.h
View File

@ -97,7 +97,6 @@ int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd,
*/
VerilogTestbenchOption options;
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_dut_module(cmd_context.option_value(cmd, opt_dut_module));
options.set_fabric_netlist_file_path(
cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_reference_benchmark_file_path(
@ -118,6 +117,10 @@ int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd,
cmd_context.option_value(cmd, opt_default_net_type));
}
if (true == cmd_context.option_enable(cmd, opt_dut_module)) {
options.set_dut_module(cmd_context.option_value(cmd, opt_dut_module));
}
/* If pin constraints are enabled by command options, read the file */
PinConstraints pin_constraints;
if (true == cmd_context.option_enable(cmd, opt_pcf)) {
@ -170,7 +173,6 @@ int write_preconfigured_fabric_wrapper_template(
*/
VerilogTestbenchOption options;
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_dut_module(cmd_context.option_value(cmd, opt_dut_module));
options.set_fabric_netlist_file_path(
cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_explicit_port_mapping(
@ -181,6 +183,10 @@ int write_preconfigured_fabric_wrapper_template(
cmd_context.option_enable(cmd, opt_include_signal_init));
options.set_print_formal_verification_top_netlist(true);
if (true == cmd_context.option_enable(cmd, opt_dut_module)) {
options.set_dut_module(cmd_context.option_value(cmd, opt_dut_module));
}
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(
cmd_context.option_value(cmd, opt_default_net_type));

3
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -88,6 +88,9 @@ void print_verilog_testbench_fpga_instance(
module_manager.find_module_port(core_module, module_port.get_name());
if (!module_manager.valid_module_port_id(core_module,
core_module_port)) {
/* Print the wire for the dummy port */
fp << generate_verilog_port(VERILOG_PORT_WIRE, module_port) << ";"
<< std::endl;
continue;
}
}