320 Commits

Author	SHA1	Message	Date
tangxifan	e9adb4fdbc	add preconfig top module Verilog generation	2020-02-26 20:38:01 -07:00
tangxifan	25e0583636	add io location map data structure and start porting verilog testbench generator	2020-02-26 17:10:57 -07:00
tangxifan	60f40a9657	use constant module manager as much as possible in Verilog writer	2020-02-16 16:35:26 -07:00
tangxifan	11775c370b	bring FPGA top module verilog writer online. Fabric Verilog generator done	2020-02-16 16:18:14 -07:00
tangxifan	e37ac8a098	add grid module Verilog writer	2020-02-16 16:04:41 -07:00
tangxifan	c20caa1fa3	routing module Verilog writer is online	2020-02-16 14:47:54 -07:00
tangxifan	c6c3ef71f3	adapt all the Verilog submodule writers and bring it onlien	2020-02-16 13:35:18 -07:00
tangxifan	99c3712b6f	adapt Verilog wire module writer	2020-02-16 12:59:37 -07:00
tangxifan	5cc68b0730	adapt LUT Verilog writer	2020-02-16 12:45:58 -07:00
tangxifan	105ccabecc	adapt memroy writer for verilog	2020-02-16 12:41:43 -07:00
tangxifan	c9d8120ae0	adapt Verilog mux writer	2020-02-16 12:35:41 -07:00
tangxifan	a88c4bc954	add decode utils to libopenfpga and adapt local decoder writer in Verilog	2020-02-16 12:21:59 -07:00
tangxifan	3efd1a2a6d	print verilog module writer online	2020-02-16 12:04:03 -07:00
tangxifan	cf34339e96	adapt essential gates for submodule generation	2020-02-16 11:57:19 -07:00
tangxifan	2eba882332	put verilog submodules online. ready to bring the how submodule writer online	2020-02-16 11:41:20 -07:00
tangxifan	4cb61e2138	bring preprocessing flag Verilog netlists online	2020-02-16 00:03:24 -07:00
tangxifan	0d5292ad0d	adapt verilog writer utils	2020-02-15 23:26:59 -07:00
tangxifan	bf54be3d00	add option data structure for FPGA Verilog	2020-02-15 21:39:47 -07:00
tangxifan	8b0df8632c	bring fpga verilog create directory online	2020-02-15 20:38:45 -07:00
tangxifan	622c7826d1	start transplanting fpga_verilog	2020-02-15 15:03:00 -07:00