[core] debugging
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3c6a4d34d8
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@ -877,7 +877,7 @@ static void print_verilog_top_testbench_ports(
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* pulled up */
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BasicPort config_all_done_port(std::string(TOP_TB_CONFIG_ALL_DONE_PORT_NAME),
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1);
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fp << generate_verilog_port(VERILOG_PORT_REG, config_all_done_port) << ";"
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fp << generate_verilog_port(VERILOG_PORT_WIRE, config_all_done_port) << ";"
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<< std::endl;
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/* Programming clock: same rule applied as the configuration done ports */
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@ -1277,12 +1277,12 @@ static void print_verilog_top_testbench_generic_stimulus(
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BasicPort curr_cfg_pin(config_done_port.get_name(),
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config_done_port.pins()[pin],
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config_done_port.pins()[pin]);
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if (pin > 1) {
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if (pin > 0) {
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fp << " & ";
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}
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fp << generate_verilog_port(VERILOG_PORT_CONKT, curr_cfg_pin);
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}
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fp << ";";
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fp << ";" << std::endl;
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/* Generate stimuli waveform for multiple user-defined operating clock signals
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*/
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@ -1692,10 +1692,20 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
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fp << ";";
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fp << std::endl;
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fp << "\t";
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fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " <= 0";
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fp << ";";
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fp << std::endl;
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if (num_prog_clocks == 1) {
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fp << "\t";
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fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " <= 0";
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fp << ";";
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fp << std::endl;
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} else {
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VTR_ASSERT(num_prog_clocks > 1);
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for (size_t iclk = 0; iclk < num_prog_clocks; ++iclk) {
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fp << "\t";
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fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << iclk << " <= 0";
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fp << ";";
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fp << std::endl;
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}
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}
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std::vector<size_t> bit_skip_values(bit_skip_reg.get_width(),
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fast_configuration ? 1 : 0);
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@ -1761,9 +1771,6 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
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fp << "\t";
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fp << "end";
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fp << std::endl;
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fp << "end";
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fp << std::endl;
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} else {
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VTR_ASSERT(num_prog_clocks > 1);
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for (size_t iclk = 0; iclk < num_prog_clocks; ++iclk) {
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@ -1781,10 +1788,10 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
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config_protocol.prog_clock_pins()[iclk]);
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fp << "\t\t";
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fp << "if (";
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bool first_pin = false;
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bool first_pin = true;
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for (size_t ccff_head_idx : ccff_head_indices) {
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if (!first_pin) {
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fp << " & ";
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fp << " && ";
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}
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fp << generate_verilog_constant_values(
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std::vector<size_t>(1, bit_value_to_skip));
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@ -1792,6 +1799,7 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
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fp << TOP_TB_BITSTREAM_MEM_REG_NAME << "["
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<< TOP_TB_BITSTREAM_ITERATOR_REG_NAME << "][" << ccff_head_idx
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<< "]";
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first_pin = false;
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}
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fp << ")";
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fp << " begin";
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@ -1835,11 +1843,10 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
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fp << "\t";
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fp << "end";
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fp << std::endl;
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fp << "end";
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fp << std::endl;
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}
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}
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fp << "end";
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fp << std::endl;
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BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME) +
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std::string(TOP_TB_CLOCK_REG_POSTFIX),
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