7f426d5939
add commands
2024-08-02 03:10:10 -07:00
48a386c9b6
add read and write uniqueblocks commands
2024-08-02 01:43:01 -07:00
0d9f1a3c6b
Forward searching the config bit + some minor refactor
2024-07-28 19:12:34 -07:00
2a3d69aded
Update code based on feedback
2024-07-28 02:37:15 -07:00
cbe9a46f95
Format and update doc
2024-07-28 00:02:20 -07:00
933155b08f
Update test flow
2024-07-27 23:52:54 -07:00
e60777d23e
Use Bitstream Setting XML
2024-07-26 01:36:49 -07:00
2ef362d53d
Init support overwriting bitstream
2024-07-25 17:40:46 -07:00
96bdcc8b35
[core] code format
2024-07-09 22:54:55 -07:00
27e29f949c
[core] fixed a bug where the pin idx of global net on rr graph is not well annotated
2024-07-09 22:53:12 -07:00
fe06c2f2b1
[core] code format
2024-07-08 16:18:58 -07:00
7bd60f5f7d
[core] support perimeter cb when identify pins of I/Os tiles
2024-07-08 12:39:54 -07:00
703cbddc9e
[core] code format
2024-07-06 12:14:57 -07:00
1f8c2436ef
[core] now constant_undriven_inputs are force to enable when perimeter_cb is selected
2024-07-04 20:46:38 -07:00
72ee39f178
[core] add new command line option 'constant_undriven_inputs'
2024-07-04 20:39:02 -07:00
a85a6f1674
[core] code format
2024-07-01 17:57:10 -07:00
70428fd969
[lib] add sanity checks on global port name and clock network's global port name
2024-07-01 17:56:29 -07:00
3afb92d6a5
[core] code format
2024-06-30 22:48:15 -07:00
1c69365938
[core] debugging
2024-06-28 18:17:38 -07:00
5cfd23747b
[core] code format
2024-06-28 13:47:03 -07:00
7892c2340c
[core] add a new option 'disable_unused_trees' to route clock rr graph
2024-06-27 12:01:54 -07:00
ac1ad52795
[core] code format
2024-06-26 22:47:29 -07:00
5d0b0b9a8c
[core] now global nets mapping are applied to clock routing
2024-06-26 22:46:12 -07:00
7bcbd8a88b
[core] code format
2024-06-25 11:44:50 -07:00
2193f108ee
[core] add debugging messages
2024-06-21 18:42:35 -07:00
7848bdaeac
[core] code format
2024-05-09 22:50:49 -07:00
5f37d63061
[core] fixed a bug where incoming edges are not built after loading rr_graph in vpr
2024-05-09 19:38:26 -07:00
bf24382f19
[core] code format
2024-05-02 18:33:07 -07:00
a2fb84dfa9
[core] add fabric hierarchy writer
2024-05-02 18:30:20 -07:00
4d3447f773
[core] rework fabric hierarchy writer
2024-05-02 18:05:38 -07:00
79970719b4
[core] fixed a bug where regex breaks
2024-04-11 14:59:14 -07:00
f63ea06c4e
[core] now support regular expression in module name for fabric pin physical location output
2024-04-11 14:30:27 -07:00
6f94399767
[core] code format
2024-04-10 22:53:52 -07:00
971f0e8838
[core] add a new option '--show_invalid_side'
2024-04-10 22:52:36 -07:00
58708ff727
[core] syntax
2024-04-10 20:08:02 -07:00
f9f7d42d93
[core] add port side attribute and set them when buidling grid/cb/sb modules
2024-04-10 17:10:06 -07:00
47baaff94c
[core] rename command name to 'write_fabric_pin_physical_location`` and start developing exec func
2024-04-10 13:30:02 -07:00
f1334645db
[core] added a new command write_pin_physical_location
2024-04-10 13:07:49 -07:00
00de794967
[core] code format
2024-03-29 10:58:48 -07:00
981828c39c
[core] add a new opton ``--dump_waveform`` to command ``write_preconfigured_fabric_wrapper``
2024-03-29 10:57:45 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
59deb97d5d
[core] code format
2024-01-12 14:17:10 -08:00
f1e3d53da6
[core] fixed a bug where pb pin fixup may fail when subtile capacities are not same
2024-01-12 14:16:07 -08:00
bacd845139
[core] code format
2023-12-08 13:41:41 -08:00
5e181cbe72
[core] add a new option for simulator type to verilog full testbench generator
2023-12-08 13:07:25 -08:00
649d44b2d8
[core] code format
2023-11-02 16:33:55 -07:00
36fa020c15
[core] syntax
2023-11-02 16:33:19 -07:00
75e9e98e5d
[core] add two new commands to output testbench parts
2023-11-02 16:06:48 -07:00
ae63c9d441
[core] code format
2023-10-06 17:28:25 -07:00
1e8bf1cece
[core] deploy options
2023-10-06 17:28:02 -07:00
f30663f708
[core] code format
2023-10-06 14:08:09 -07:00
80856f1b70
[core] adding new options and rewrite options for bitfile writer
2023-10-06 13:54:29 -07:00
a15db83267
[core] code format
2023-09-26 11:41:11 -07:00
ea91182216
[core] check option conflicts
2023-09-26 11:40:42 -07:00
edb0e687f1
[core] code format
2023-09-23 12:15:53 -07:00
11de8965a8
[core] fixed some bugs
2023-09-23 12:15:31 -07:00
860cfd53c6
[core] fixed critical bugs in renaming modules
2023-09-23 11:51:31 -07:00
c105b56bf0
[core] code format
2023-09-18 23:31:27 -07:00
43fd08a3fe
[core] fixed a bug
2023-09-18 23:31:09 -07:00
c6175aa514
[core] code format
2023-09-17 22:37:48 -07:00
ef97127c63
[core] fixed some bugs in testbenches when renaming top modules
2023-09-17 22:34:00 -07:00
c14277a674
[core] fixing bugs
2023-09-17 17:57:57 -07:00
d5152dc16d
[core] fixed a bug on the hierarchy writer
2023-09-17 17:42:25 -07:00
4ccb4737be
[core] code format
2023-09-17 17:33:10 -07:00
f79da76656
[core] supporting renaming on all the verilog modules
2023-09-17 17:29:11 -07:00
72a3c05747
[core] code format
2023-09-17 13:29:30 -07:00
ccd4c1861b
[core] developing new command to write module naming rules
2023-09-16 19:37:06 -07:00
6fc2924438
[core] syntax
2023-09-16 18:16:30 -07:00
37573abc22
[core] code format
2023-09-15 23:32:40 -07:00
c85c64eb5a
[core] syntax
2023-09-15 23:30:34 -07:00
bc407e5d69
[core] code complete for rename modules
2023-09-15 23:22:31 -07:00
2a45b49890
[core] developing renaming commands. options and functions
2023-09-15 19:15:18 -07:00
dfe5447e2a
[core] format
2023-08-25 15:21:24 -07:00
b8c66b06a0
[core] syntax
2023-08-25 15:17:52 -07:00
94d80a9b7c
[core] code format
2023-08-08 16:28:56 -07:00
867da98d3f
[core] update to use latest api from vpr upstream
2023-08-08 16:28:19 -07:00
bb945b2816
Merge branch 'master' into openfpga-issue-1256
2023-08-07 13:49:19 -07:00
d3895c3dc0
[core] code format
2023-08-03 17:34:25 -07:00
87f2822ef8
[core] working on logical and physical children
2023-08-02 19:46:27 -07:00
470ab84489
[core] developing group config block support for routing module
2023-08-01 22:57:22 -07:00
53050b94ab
[core] developing memory group modules in grid modules
2023-08-01 17:50:03 -07:00
23643f3fb1
[core] developing the physical memory block builder
2023-07-31 22:57:26 -07:00
2d2b8f67aa
[core] adding new option '--group_config_block' to command 'build_fabric'
2023-07-31 17:32:48 -07:00
19ed9ea669
Merge branch 'master' into openfpga-issue-1256
2023-07-26 10:32:30 -07:00
de6956530f
[core] disable pnr sdc for tile-based fabric
2023-07-25 15:38:41 -07:00
3745897ff6
[core] fixed a few bugs
2023-07-24 16:10:29 -07:00
48b0ba8b78
[core] format
2023-07-24 15:00:26 -07:00
812473ef04
[core] fixed the bug on io location map for tiled top module
2023-07-24 14:50:39 -07:00
da36b735c6
[core] syntax
2023-07-24 12:13:45 -07:00
93c5a68592
[core] developing top-level nets for tiles
2023-07-21 23:21:53 -07:00
39934f9d16
Address issue 1256
2023-07-20 22:34:18 -07:00
b70f7fb1b6
[core] now option conflicts in command 'build_fabric' can error out
2023-07-20 21:22:07 -07:00
6607bb7e48
[core] now fpga verilog supports tile modules
2023-07-18 22:35:22 -07:00
ba4b7e3522
[core] developing tile module builder
2023-07-16 15:18:09 -07:00
c2ef5ca408
[core] developing top-left style tile info
2023-07-14 22:48:44 -07:00
091ac88c7e
[lib] code format
2023-07-14 12:16:40 -07:00
3bc959dcec
[lib] create tile config lib and start integration to core
2023-07-14 12:13:31 -07:00
c58035dbd4
[core] start developing option --group_tile for build_fabric
2023-07-14 11:01:04 -07:00
3de4d3fc09
[core] add a new command 'write_fabric_key' and now writer supports module-level keys
2023-07-08 18:12:51 -07:00
ddfb0c4afd
[core] now mock fpga top supports fpga core wrapper
2023-06-26 15:06:11 -07:00
Lin
chungshien-chai
tangxifan
chungshien
Chung Shien Chai