Update test flow
This commit is contained in:
chungshien-chai
parent
0ff0c3445e
commit
933155b08f
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@ -105,16 +105,18 @@ static void read_xml_non_fabric_bitstream_setting(
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/********************************************************************
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* Parse XML description for a bit setting under a <bit> XML node
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*******************************************************************/
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static void read_xml_bit_setting(
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pugi::xml_node& xml_bit, const pugiutil::loc_data& loc_data,
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static void read_xml_overwrite_bit_setting(
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pugi::xml_node& xml_overwrite_bitstream, const pugiutil::loc_data& loc_data,
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openfpga::BitstreamSetting& bitstream_setting) {
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const std::string& path_attr =
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get_attribute(xml_bit, "path", loc_data).as_string();
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const std::string& value_attr =
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get_attribute(xml_bit, "value", loc_data).as_string();
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VTR_ASSERT_SAFE(value_attr == "0" || value_attr == "1");
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/* Add to bit */
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bitstream_setting.add_path_bit_setting(path_attr, value_attr == "1");
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for (pugi::xml_node xml_bit : xml_overwrite_bitstream.children()) {
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const std::string& path_attr =
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get_attribute(xml_bit, "path", loc_data).as_string();
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const std::string& value_attr =
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get_attribute(xml_bit, "value", loc_data).as_string();
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VTR_ASSERT(value_attr == "0" || value_attr == "1");
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/* Add to bit */
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bitstream_setting.add_path_bit_setting(path_attr, value_attr == "1");
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}
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}
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/********************************************************************
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@ -132,9 +134,9 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(
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if ((xml_child.name() != std::string("pb_type")) &&
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(xml_child.name() != std::string("interconnect")) &&
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(xml_child.name() != std::string("non_fabric")) &&
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(xml_child.name() != std::string("bit"))) {
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(xml_child.name() != std::string("overwrite_bitstream"))) {
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bad_tag(xml_child, loc_data, Node,
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{"pb_type | interconnect | non_fabric | bit"});
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{"pb_type | interconnect | non_fabric | overwrite_bitstream"});
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}
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if (xml_child.name() == std::string("pb_type")) {
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@ -147,8 +149,8 @@ openfpga::BitstreamSetting read_xml_bitstream_setting(
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read_xml_non_fabric_bitstream_setting(xml_child, loc_data,
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bitstream_setting);
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} else {
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VTR_ASSERT_SAFE(xml_child.name() == std::string("bit"));
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read_xml_bit_setting(xml_child, loc_data, bitstream_setting);
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VTR_ASSERT_SAFE(xml_child.name() == std::string("overwrite_bitstream"));
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read_xml_overwrite_bit_setting(xml_child, loc_data, bitstream_setting);
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}
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}
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@ -68,8 +68,14 @@ int call_external_command(const Command& cmd,
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VTR_LOG("Processer is not available");
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return CMD_EXEC_FATAL_ERROR;
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}
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return system(cmd_ss.c_str());
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int status = system(cmd_ss.c_str());
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if (status & 0xFF) {
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// First 8 bits are system signals
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return 1;
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}
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// real return was actually shifted 8 bits
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return status >> 8;
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}
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} /* end namespace openfpga */
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@ -15,8 +15,8 @@ echo -e "Testing bitstream generation for an 48x48 FPGA device";
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run-task fpga_bitstream/generate_bitstream/configuration_chain/device_48x48 $@
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run-task fpga_bitstream/generate_bitstream/ql_memory_bank_shift_register/device_48x48 $@
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echo -e "Testing bitstream generation for an 4x4 FPGA device (overwrite IO tile bits)";
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run-task fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_PathBitSetting $@
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echo -e "Testing bitstream generation for an 4x4 FPGA device (randomly overwrite fabric bits)";
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run-task fpga_bitstream/overwrite_bitstream/device_4x4 $@
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echo -e "Testing bitstream generation for an 96x96 FPGA device";
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run-task fpga_bitstream/generate_bitstream/configuration_chain/device_96x96 $@
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@ -1,9 +0,0 @@
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<!--
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////////////////////////////////////////////////////////////////////////////////
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# THIS FILE WAS AUTOMATICALLY GENERATED FROM DO NOT EDIT
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////////////////////////////////////////////////////////////////////////////////
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-->
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<openfpga_bitstream_setting>
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<bit value="0" path="fpga_top.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem[0]"/>
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<bit value="0" path="fpga_top.grid_io_bottom_3__0_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFFR_mem[0]"/>
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</openfpga_bitstream_setting>
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@ -1,79 +0,0 @@
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# This file is copied from fix_device_example_script.openfpga
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Read OpenFPGA bitstream settings
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read_openfpga_bitstream_setting -f ${OPENFPGA_BITSTREAM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing #--verbose
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# Write the fabric hierarchy of module graph to a file
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# This is used by hierarchical PnR flows
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write_fabric_hierarchy --file ./fabric_hierarchy.txt
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
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write_fabric_bitstream --file fabric_bitstream.xml --format xml
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
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# Write the Verilog testbench for FPGA fabric
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - Must specify the reference benchmark file if you want to output any testbenches
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
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write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
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write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ./SDC
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
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# Write the SDC to run timing analysis for a mapped FPGA fabric
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write_analysis_sdc --file ./SDC_analysis
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -16,10 +16,10 @@ timeout_each_job = 20*60
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fpga_flow=vpr_blif
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_PathBitSetting/config/write_xml.openfpga
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_bitstream/overwrite_bitstream/device_4x4/config/test.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/configuration_chain/device_4x4_PathBitSetting/config/bitstream_annotation.xml
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openfpga_bitstream_setting_file=bitstream_annotation.xml
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openfpga_vpr_device_layout=4x4
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[ARCHITECTURES]
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@ -0,0 +1,53 @@
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# This file is copied from fix_device_example_script.openfpga
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ext_exec --command "python3 ../../../../config/test.py run_golden"
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ext_exec --command "python3 ../../../../config/test.py generate_testcase"
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Read OpenFPGA bitstream settings
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read_openfpga_bitstream_setting -f ${OPENFPGA_BITSTREAM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing #--verbose
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.xml --format xml
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ext_exec --command "python3 ../../../../config/test.py validate"
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# Finish and exit OpenFPGA
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exit
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@ -0,0 +1,120 @@
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import xml.etree.ElementTree as ET
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import sys
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import shutil
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import os
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import random
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random.seed()
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assert len(sys.argv) >= 2
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assert sys.argv[1] in ["run_golden", "generate_testcase", "validate"]
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TEST_BIT_COUNT = 200
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def read_fabric_bitstream_xml(file) :
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bit_count = 0
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tree = ET.parse(file)
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root = tree.getroot()
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assert root.tag == "fabric_bitstream", "Root tag is not 'fabric_bitstream', but '%s'" % root.tag
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for region in root :
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assert region.tag == "region", "fabric_bitstream child node tag is not 'region', but '%s'" % region.tag
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for bit in region :
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assert bit.tag == "bit", "region child node tag is not 'bit', but '%s'" % bit.tag
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assert "path" in bit.attrib, "Attribute 'path' does not exist in bit node"
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assert "value" in bit.attrib, "Attribute 'value' does not exist in bit node"
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assert bit.attrib["value"] in ["0", "1"]
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bit_count += 1
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return [tree, bit_count]
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def read_bitstream_annotation_xml(file) :
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xml = {}
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tree = ET.parse(file)
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root = tree.getroot()
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assert root.tag == "openfpga_bitstream_setting", "Root tag is not 'openfpga_bitstream_setting', but '%s'" % root.tag
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for overwrite_bitstream in root :
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assert overwrite_bitstream.tag == "overwrite_bitstream", "openfpga_bitstream_setting child node tag is not 'overwrite_bitstream', but '%s'" % overwrite_bitstream.tag
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for bit in overwrite_bitstream :
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assert bit.tag == "bit", "overwrite_bitstream child node tag is not 'bit', but '%s'" % bit.tag
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assert "path" in bit.attrib, "Attribute 'path' does not exist in bit node"
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assert "value" in bit.attrib, "Attribute 'value' does not exist in bit node"
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path = bit.attrib["path"]
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assert path not in xml
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index = path.rfind("[")
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assert index != -1
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path = "%s.mem_out%s" % (path[:index], path[index:])
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assert path not in xml
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assert bit.attrib["value"] in ["0", "1"]
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xml[path] = bit.attrib["value"]
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return xml
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if sys.argv[1] == "run_golden" :
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openfpga_exe = os.path.abspath("../../../../../../../../../build/openfpga/openfpga")
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assert os.path.exists(openfpga_exe)
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shutil.rmtree("golden", ignore_errors=True)
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os.mkdir("golden")
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original_openfpga = open("and2_run.openfpga")
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golden_openfpga = open("golden/and2_run.openfpga", "w")
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for line in original_openfpga :
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if line.find("ext_exec") == 0 :
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pass
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else :
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golden_openfpga.write(line)
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golden_openfpga.close()
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original_openfpga.close()
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bitstream_annotation = open("golden/bitstream_annotation.xml", "w")
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bitstream_annotation.write("<openfpga_bitstream_setting/>\n")
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bitstream_annotation.close()
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shutil.copyfile("and2.blif", "golden/and2.blif")
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shutil.copyfile("and2_ace_out.act", "golden/and2_ace_out.act")
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cmd = "cd golden && %s -batch -f and2_run.openfpga > golden.log" % (openfpga_exe)
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assert os.system(cmd) == 0
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elif sys.argv[1] == "generate_testcase" :
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(tree, bit_count) = read_fabric_bitstream_xml("golden/fabric_bitstream.xml")
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random_bits = []
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while len(random_bits) != TEST_BIT_COUNT :
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bit = random.randint(0, bit_count - 1)
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if bit not in random_bits :
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random_bits.append(bit)
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bitstream_annotation = open("bitstream_annotation.xml", "w")
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bitstream_annotation.write("<openfpga_bitstream_setting>\n")
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bitstream_annotation.write(" <overwrite_bitstream>\n")
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index = 0
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for region in tree.getroot() :
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for bit in region :
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if index in random_bits :
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path = bit.attrib["path"]
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value = bit.attrib["value"]
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assert value in ["0", "1"]
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path = path.replace(".mem_out[", "[")
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bitstream_annotation.write(" <bit value=\"%s\" path=\"%s\"/>\n" % ("1" if value == "0" else "0", path))
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index += 1
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bitstream_annotation.write(" </overwrite_bitstream>\n")
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bitstream_annotation.write("</openfpga_bitstream_setting>\n")
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bitstream_annotation.close()
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else :
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gtree = ET.parse("golden/fabric_bitstream.xml")
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tree = ET.parse("fabric_bitstream.xml")
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bitstream_annotation = read_bitstream_annotation_xml("bitstream_annotation.xml")
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status = 0
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checked_count = 0
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for gregion, region in zip(gtree.getroot(), tree.getroot()) :
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for gbit, bit in zip(gregion, region) :
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assert bit.attrib["path"] == gbit.attrib["path"]
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path = bit.attrib["path"]
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if path in bitstream_annotation :
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# This is something we want to overwrite, hence the value should
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# Same in the annotation file
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# Not same in golden fabric
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assert bit.attrib["value"] != gbit.attrib["value"]
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assert bit.attrib["value"] == bitstream_annotation[path]
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else :
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# This is not what we want to overwrite
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# Hence the value should same in golden fabric
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assert bit.attrib["value"] == gbit.attrib["value"]
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exit(0)
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