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Update doc

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chungshien-chai 2024-07-26 13:43:31 -07:00
parent fbe5ae6bd3
commit 0ff0c3445e
1 changed files with 27 additions and 3 deletions
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docs/source/manual/file_formats/bitstream_setting.rst
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@ -16,6 +16,7 @@ This can define a hard-coded bitstream for a reconfigurable resource in FPGA fab
<non_fabric name="<string>" file="<string>">
<pb name="<string>" type="<string>" content="<string>"/>
</non_fabric>
<bit value="<0 or 1>" path="<string>"/>
</openfpga_bitstream_setting>
pb_type-related Settings
@ -75,7 +76,7 @@ The following syntax are applicable to the XML definition tagged by ``interconne
The default path can be either ``iopad.inpad`` or ``ff.Q`` which corresponds to the first input and the second input respectively.
non_fabric-related Settings
^^^^^^^^^^^^^^^^^^^^^^^^
^^^^^^^^^^^^^^^^^^^^^^^^^^^
This is special syntax to extract PB defined parameter or attribute and save the data into dedicated JSON file outside of fabric bitstream
@ -97,7 +98,7 @@ The following syntax are applicable to the XML definition tagged by ``non_fabric
file="bram.json"
.. option:: ``pb`` child element name="<string: pb_type child name>"
.. option:: pb child element name="<string: pb_type child name>"
Together with ``pb_type`` top level name, that is the source of the ``pb_type`` bitstream
@ -112,6 +113,29 @@ The following syntax are applicable to the XML definition tagged by ``non_fabric
The final ``pb_type`` name is "bram.bram_lr[mem_36K_tdp].mem_36K"
.. option:: ``pb`` child element content="<string>"
.. option:: pb child element content="<string>"
The content of the ``pb_type`` data to be extracted. For example, ``content=".param INIT_i"`` means that the data will be extracted from the ``.param INIT_i`` line defined under the ``.blif model``.
bit-related Settings
^^^^^^^^^^^^^^^^^^^^
This is to allow user to set particular bit using full path in the hierarchy of FPGA fabric
The following syntax are applicable to the XML definition tagged by ``bit`` in bitstream setting files.
.. option:: value="<0 or 1>"
The boolean ``0`` or ``1`` that will be set. For example,
.. code-block:: xml
value="0"
.. option:: path="<string>"
``path`` represents the location of this block in FPGA fabric, i.e., the full path in the hierarchy of FPGA fabric.
.. code-block:: xml
path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5[0]"