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OpenFPGA
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5,528 Commits 70 Branches 8 Tags 105 MiB
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950 Commits

Author SHA1 Message Date
tangxifan 3656154913 [engine] fixed syntax errors 2022-08-29 21:17:48 -07:00
tangxifan 2321ea6274 [engine] complete the code required to output rr_gsb with options 2022-08-29 20:44:16 -07:00
tangxifan 12a30196e0 [engine] updating gsb writer; Unfinished!!! 2022-08-29 16:58:48 -07:00
tangxifan b9abdbc5d4 [engine] enable verbose output 2022-08-27 19:59:57 -07:00
tangxifan e9d6e7e38a [engine] update vtr and enable more debugging info 2022-08-27 19:12:43 -07:00
tangxifan 0c2b49ddb9 [engine] remove debugging log output 2022-08-27 13:06:05 -07:00
tangxifan 25f6c529e0 [engine] fixed syntax errors when using clang 2022-08-25 09:58:43 -07:00
tangxifan b432ac05b4 [script] fixed typo on IPO options 2022-08-24 21:51:29 -07:00
tangxifan f853040875 [script] enable IPO in cmakefile 2022-08-24 14:34:33 -07:00
tangxifan ba6ae05091 [engine] update vtr and add in_edge checks to link_arch 2022-08-24 12:22:20 -07:00
tangxifan d1edc51165 [engine] clean up header files that include rr_graph_obj 2022-08-23 18:38:21 -07:00
tangxifan b3e4a06969 [engine] adapt vpr wrapper to the latest main.cpp from vtr 2022-08-23 14:28:05 -07:00
tangxifan 892770a8fb [engine] debugging subtile index failures 2022-08-23 14:13:10 -07:00
tangxifan 0a6b794ef0 [engine] fixed bugs in subtiles. Revisited the usage of client functions 2022-08-23 12:35:04 -07:00
tangxifan 019e663e12 [engine] fixing the bugs on building global nets to sub tile pins 2022-08-23 11:58:44 -07:00
tangxifan 10cefebca8 [engine] fixing bugs on using subtile index 2022-08-23 11:00:23 -07:00
tangxifan ba0ddd01d3 [engine] fixing the bugs on subtiles 2022-08-23 10:52:05 -07:00
tangxifan c17e5d46ab [engine] fixed a bug due to the API of subtile data structure 2022-08-22 21:44:05 -07:00
tangxifan 5d6a90d983 [engine] remove compile warnings 2022-08-22 20:59:50 -07:00
tangxifan 800ce6a290 [engine] avoid function naming conflicts 2022-08-18 19:33:56 -07:00
tangxifan 903dd6cef6 [engine] remove warnings 2022-08-18 15:56:18 -07:00
tangxifan a52597361b [script] remove duplicated libraries in dependency list for some libopenfpga 2022-08-18 11:34:01 -07:00
tangxifan e9c4d102c1 [engine] rename files to avoid conflicts with VPR files 2022-08-17 20:01:50 -07:00
tangxifan 40100c1ba3 [engine] remove warnings 2022-08-17 19:07:49 -07:00
tangxifan cb4b106d4e [engine] correcting syntax errors 2022-08-17 16:36:14 -07:00
tangxifan dfe30df462 [engine] resolve compilation warnings 2022-08-17 16:32:21 -07:00
tangxifan e0ae851e28 [engine] correcting compilation errors due to vpr upgrade 2022-08-17 16:25:12 -07:00
tangxifan ce32c3b30b [engine] fixing api errors 2022-08-17 14:47:14 -07:00
tangxifan 3c2bf5159b [engine] use new API to get node side 2022-08-17 14:38:40 -07:00
tangxifan 3c12810ad9 [engine] debugging 2022-08-17 14:37:13 -07:00
tangxifan 8f1aac885e [engine] fixing mismatches in APIs 2022-08-17 14:19:02 -07:00
tangxifan 4e871be357 [engine] adapt the use of API in RRGraph for annotation functions 2022-08-17 10:50:16 -07:00
tangxifan 01d53db484 [script] Adapt timing analysis APIs 2022-08-17 10:28:58 -07:00
tangxifan ade8f43a36 [engine] Updating RRGraph Annotation and VTr 2022-08-17 10:16:55 -07:00
tangxifan 716929536d [engine] adapting source files for new APIs in VTR 2022-08-17 09:54:31 -07:00
tangxifan d3d81f0b18 [engine] keep adapting to latest VTR 2022-08-16 21:05:50 -07:00
tangxifan 0c329866da [engine] Use RRGraphView in openfpga source codes 2022-08-16 16:48:32 -07:00
tangxifan ce7204daec [engine] debugging 2022-08-16 16:35:08 -07:00
tangxifan c1256ae818 [engine] added command 'pcf2place' to openfpga 2022-07-28 11:30:36 -07:00
tangxifan 2a5bffa6b9 [engine] developing pcf2place integration to openfpga 2022-07-28 10:30:43 -07:00
tangxifan 1c9da96f59 [lib] move io_location_map to libpcf 2022-07-26 16:00:28 -07:00
tangxifan 27fea8bbbe [lib] Merge librepackdc into libpcf 2022-07-26 15:54:32 -07:00
tangxifan 23f98d6a3b [engine] fixed a few bugs 2022-07-26 13:55:29 -07:00
tangxifan 85bcb36f34 [engine] fix compiler errors 2022-07-26 12:25:40 -07:00
tangxifan 0862eceed0 [engine] add an XML write to io location map: In the long run, we should decouple the writer function from the data structure!!! 2022-07-26 12:17:45 -07:00
taoli4rs 3762a3aae4 Code clean up based on review. 2022-07-20 14:34:44 -07:00
taoli4rs cfc0d08060 Add constrain_pin_location command in openfpga; add full flow test. 2022-07-20 11:51:00 -07:00
tangxifan a7e87b9432 [FPGA-Bitstream] note limitations 2022-05-25 18:38:01 +08:00
tangxifan ffac5a66e1 [FPGA-Bitstream] Now encode address bits to save memory in bitstream database 2022-05-25 17:45:08 +08:00
tangxifan bf1a81fbb5 [FPGA-bitstream] add timer to computing intensive functions 2022-05-25 14:52:32 +08:00
tangxifan a20f6eaf06 [Engine] Fixed a few bugs 2022-04-10 21:29:38 +08:00
tangxifan 755be78b39 [Engine] Now GSB output file contains segments name and pin name in SB module 2022-04-10 21:22:30 +08:00
tangxifan 6171abdf95 [FPGA-Bitstream] Now report_bitstream_distribution includes fabric bitstream stats 2022-03-29 19:41:15 +08:00
tangxifan 4d67864c2c [Engine] Now global port can be connected partial pins of a tile port 2022-03-20 11:36:03 +08:00
tangxifan 8ab090651a [FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports 2022-03-16 20:51:37 +08:00
tangxifan 235887e03a [FPGA-Verilog] Fixed a bug on config-enable signals 2022-02-23 22:35:23 -08:00
tangxifan 086642d134 [FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly 2022-02-23 15:33:24 -08:00
tangxifan 1c18d14ad5 [FPGA-Verilog] Add big/little endian support to output ports 2022-02-19 09:23:48 -08:00
tangxifan 3e43a60fdc [FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks 2022-02-19 09:15:38 -08:00
tangxifan 671188dfa4 [FPGA-Verilog] Now support big/little-endian in bus group 2022-02-18 23:05:03 -08:00
tangxifan 790715f46a [FPGA-Verilog] Fixing bugs when using bus group in full testbench generator 2022-02-18 15:41:35 -08:00
tangxifan 401f673f16 [FPGA-Verilog] Streamline codes by using APIs 2022-02-18 14:47:36 -08:00
tangxifan c16ea8d082 [FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches 2022-02-18 14:34:32 -08:00
tangxifan a4dc86a33d [FPGA-Verilog] Now output atom block name removal has a dedicated function 2022-02-18 14:30:46 -08:00
tangxifan f5dd89bbd9 [FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used 2022-02-18 14:08:03 -08:00
tangxifan 0d620888ab [FPGA-Verilog] Now instance can output bus ports with all the pins 2022-02-18 12:03:26 -08:00
tangxifan aa375fd7a4 [FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator 2022-02-18 11:31:11 -08:00
tangxifan 6da0ede9b0 [FPGA-Verilog] Adding bus group support to all Verilog testbench generators 2022-02-17 23:48:44 -08:00
tangxifan c96f0d199d [FPGA-Verilog] Adding bus group support in Verilog testbenches 2022-02-17 23:14:28 -08:00
tangxifan 38601f325b [Engine] Add bus group to OpenFPGA core 2022-02-17 17:28:55 -08:00
tangxifan e67f8ad8b2 [FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase 2022-02-15 17:19:50 -08:00
tangxifan be8f18310d [FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances 2022-02-14 17:16:26 -08:00
tangxifan d3f68db228 [FPGA-Verilog] fixing bugs in reset ports for counters in full testbenches 2022-02-14 17:00:54 -08:00
tangxifan 34e192c5ca [FPGA-Verilog] Fixed a bug on wiring FPGA global ports 2022-02-14 15:21:29 -08:00
tangxifan 8d48492ec0 [FPGA-Verilog] Add clock ports to the white list when adding postfix 2022-02-14 11:09:00 -08:00
tangxifan 5794561f7b [FPGA-Verilog] Now shared input wire/register has a postfix in full testbench 2022-02-14 10:39:27 -08:00
tangxifan 2ca73d79e4 [FPGA-Verilog] Fixed the bug on pin constraints 2022-02-13 22:08:06 -08:00
tangxifan b1377f0d34 [FPGA-Verilog] Fix syntax errors 2022-02-13 20:29:05 -08:00
tangxifan 6e132aace4 [FPGA-Verilog] Remove the prefix added by VPR in preconfigured top module 2022-02-13 20:26:21 -08:00
tangxifan fb4106de19 [FPGA-Verilog] Fixed a bug in naming mismatch 2022-02-13 20:06:35 -08:00
tangxifan a068237082 [FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks 2022-02-13 19:55:16 -08:00
tangxifan 1c94d0f285 [FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path`` 2022-02-01 13:25:09 -08:00
tangxifan f311a034bb [FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path`` 2022-02-01 12:17:02 -08:00
tangxifan 2b8e2de0c9 [FPGA-Verilog] Fix bugs 2022-01-31 14:23:04 -08:00
tangxifan 6c29c286bc [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
tangxifan 63f44adf15 [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
Emin Cetin 6c2c4e8b14 adding comment 2022-01-28 08:57:45 +03:00
Emin Cetin f9b47c3b34 missing semicolon 2022-01-27 16:49:04 +03:00
Emin Cetin 8f7ee4e338 changing condition of bitstream downloading 2022-01-27 11:49:55 +03:00
tangxifan a9a56686e2 [Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml`` 2022-01-26 11:10:29 -08:00
tangxifan a9e6b7c12e [FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled 2022-01-25 20:33:49 -08:00
tangxifan 33064ca4cf [FPGA-SDC] Add a new option ``--no_time_stamp`` to all the commands 2022-01-25 15:51:28 -08:00
tangxifan b09e13b42c [FPGA-Verilog] Fixed a bug on invalid option of a command 2022-01-25 13:45:44 -08:00
tangxifan 25143d07f1 [FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files 2022-01-25 13:37:54 -08:00
tangxifan 62b57b05d2 [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
nadeemyaseen-rs dbe8616837 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-12-23 00:00:22 +05:00
Tarachand Pagarani 02e4ae9740 allow bitstream setting on hard blocks 2021-12-07 03:42:22 -08:00
tangxifan ff264c00a2 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-31 11:51:34 -07:00
tangxifan 91627abe12 [FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided 2021-10-30 11:53:46 -07:00
tangxifan 6586ea7816 [Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture 2021-10-11 09:40:02 -07:00