tangxifan
|
2ca73d79e4
|
[FPGA-Verilog] Fixed the bug on pin constraints
|
2022-02-13 22:08:06 -08:00 |
|
tangxifan
|
b1377f0d34
|
[FPGA-Verilog] Fix syntax errors
|
2022-02-13 20:29:05 -08:00 |
|
tangxifan
|
6e132aace4
|
[FPGA-Verilog] Remove the prefix added by VPR in preconfigured top module
|
2022-02-13 20:26:21 -08:00 |
|
tangxifan
|
fb4106de19
|
[FPGA-Verilog] Fixed a bug in naming mismatch
|
2022-02-13 20:06:35 -08:00 |
|
tangxifan
|
a068237082
|
[FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks
|
2022-02-13 19:55:16 -08:00 |
|
tangxifan
|
1c94d0f285
|
[FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path``
|
2022-02-01 13:25:09 -08:00 |
|
tangxifan
|
f311a034bb
|
[FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path``
|
2022-02-01 12:17:02 -08:00 |
|
tangxifan
|
2b8e2de0c9
|
[FPGA-Verilog] Fix bugs
|
2022-01-31 14:23:04 -08:00 |
|
tangxifan
|
6c29c286bc
|
[FPGA-Verilog] Fix a bug which cause errors
|
2022-01-31 14:06:58 -08:00 |
|
tangxifan
|
63f44adf15
|
[FPGA-Verilog] Now have a new option ``--use_relative_path``
|
2022-01-31 12:48:05 -08:00 |
Emin Cetin
|
6c2c4e8b14
|
adding comment
|
2022-01-28 08:57:45 +03:00 |
|
Emin Cetin
|
f9b47c3b34
|
missing semicolon
|
2022-01-27 16:49:04 +03:00 |
|
Emin Cetin
|
8f7ee4e338
|
changing condition of bitstream downloading
|
2022-01-27 11:49:55 +03:00 |
|
tangxifan
|
62b57b05d2
|
[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
|
2022-01-25 12:09:08 -08:00 |
|
tangxifan
|
ff264c00a2
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-31 11:51:34 -07:00 |
|
tangxifan
|
91627abe12
|
[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided
|
2021-10-30 11:53:46 -07:00 |
|
tangxifan
|
546350ae41
|
[FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks
|
2021-10-10 23:19:39 -07:00 |
|
tangxifan
|
202b50c0e3
|
[FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why
|
2021-10-10 20:57:23 -07:00 |
|
tangxifan
|
de3275e9ba
|
[FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains
|
2021-10-10 16:56:07 -07:00 |
|
tangxifan
|
6aa4991314
|
[FPGA-Verilog] Bug fix
|
2021-10-09 21:34:07 -07:00 |
|
tangxifan
|
34575f7222
|
[FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank
|
2021-10-09 20:39:45 -07:00 |
|
tangxifan
|
19a551e641
|
[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
|
2021-10-09 16:44:04 -07:00 |
|
tangxifan
|
8f5f30792f
|
[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
|
2021-10-08 15:25:37 -07:00 |
|
tangxifan
|
54a8809b3c
|
[FPGA-Verilog] Bug fix in computing clock frequency for shift register chains
|
2021-10-06 16:49:28 -07:00 |
|
tangxifan
|
27153bbc89
|
[FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition
|
2021-10-06 13:38:51 -07:00 |
|
tangxifan
|
bf473f50f8
|
[FPGA-Verilog] Correct bugs in logging clock frequencies
|
2021-10-06 11:55:57 -07:00 |
|
tangxifan
|
fcb5470baa
|
[Lib] Add validator to check if a clock is constrained in simulation settings
|
2021-10-06 11:48:23 -07:00 |
|
tangxifan
|
82ed6b177b
|
[FPGA-Verilog] Now consider clock constraints for BL/WL shift registers
|
2021-10-06 11:39:28 -07:00 |
|
tangxifan
|
2badcb58f2
|
[FPGA-Verilog] Fixed a critical bug in verilog testbench generator for QL memory bank using BL/WL register which causes misalignment in shift register loading
|
2021-10-03 16:04:47 -07:00 |
|
tangxifan
|
756b4c7dc8
|
[FPGA-Verilog] Bug fix in estimating the simulation period for QuickLogic memory bank using BL/WL shift registers
|
2021-10-03 12:11:20 -07:00 |
|
tangxifan
|
3eb601531a
|
[FPGA-Verilog] Many bug fixes
|
2021-10-02 23:39:53 -07:00 |
|
tangxifan
|
d453e6477d
|
[FPGA-Verilog] Bug fix
|
2021-10-02 22:32:57 -07:00 |
|
tangxifan
|
02af633acd
|
[FPGA-Verilog] Fixed several bugs in testbench generator which caused iVerilog errors
|
2021-10-02 22:14:15 -07:00 |
|
tangxifan
|
fa7e168137
|
[FPGA-Verilog] Now testbench generator connects global shift register clocks to FPGA ports
|
2021-10-02 22:08:14 -07:00 |
|
tangxifan
|
76d58ebaa0
|
[FPGA-Verilog] Move clock generator to generic stimuli and shift register clock period is auto tuned by programming clock period
|
2021-10-02 21:48:10 -07:00 |
|
tangxifan
|
54ec74d8d2
|
[FPGA-Verilog] Bug fix in code generator
|
2021-10-02 17:31:37 -07:00 |
|
tangxifan
|
32fc0a1692
|
[FPGA-Verilog] Upgrading verilog testbench generator for QuickLogic memory bank using BL/WL shift register
|
2021-10-02 17:25:27 -07:00 |
|
tangxifan
|
9e5debabe1
|
[FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks
|
2021-10-01 16:23:38 -07:00 |
|
tangxifan
|
2bd2788e77
|
[Engine] Upgrading testbench generator to support QuickLogic memory bank with shift registers
|
2021-10-01 11:23:40 -07:00 |
|
tangxifan
|
7b010ba0f4
|
[Engine] Support programming shift register clock in XML syntax
|
2021-10-01 11:00:38 -07:00 |
|
tangxifan
|
2d4c200d58
|
[FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists
|
2021-09-29 20:56:02 -07:00 |
|
tangxifan
|
29c351f5a4
|
[Engine] Bug fix in estimating the configuration cycles for Verilog testbench generator
|
2021-09-25 19:34:21 -07:00 |
|
tangxifan
|
a56d1f4fdb
|
[FPGA-Verilog] Upgraded testbench generator to support memory bank using flatten BL/WLs
|
2021-09-25 17:49:15 -07:00 |
|
tangxifan
|
c84c0d4a3f
|
[FPGA-Verilog] Upgrade fpga-verilog to support decoders with WLR
|
2021-09-20 17:07:26 -07:00 |
|
tangxifan
|
b787c4e100
|
[Engine] Register QL memory bank as a legal protocol
|
2021-09-09 15:06:51 -07:00 |
|
tangxifan
|
1aac3197eb
|
[FPGA-Verilog] Upgrade testbench generator to support QL memory bank
|
2021-09-05 21:38:00 -07:00 |
|
tangxifan
|
e9d29e27e5
|
[Tool] Bug fix
|
2021-07-02 15:32:30 -06:00 |
|
tangxifan
|
6e6c3e9fa4
|
[Tool] Patch the critical bug in the use of signal polarity in pin constraints
|
2021-07-02 15:26:21 -06:00 |
|
tangxifan
|
9074bffa68
|
[Tool] Support customized default value in pin constraint file
|
2021-07-01 23:43:19 -06:00 |
|
tangxifan
|
d0e4f8521f
|
[Tool] Bug fix on the reset stimuli
|
2021-07-01 19:58:54 -06:00 |
|
tangxifan
|
b5df1f9aeb
|
[Tool] Bug fix for redundant endif in netlists
|
2021-06-29 17:02:16 -06:00 |
|
tangxifan
|
b83eef47b4
|
[Tool] Bug fix for testbench generation without self checking codes
|
2021-06-29 16:27:29 -06:00 |
|
tangxifan
|
6a260cadbf
|
[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
|
2021-06-29 15:42:23 -06:00 |
|
tangxifan
|
7ac7de789e
|
[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
|
2021-06-29 15:26:40 -06:00 |
|
tangxifan
|
77dddaeb39
|
[Tool] Remove the preprocessing flags ``FORMAL_SIMULATION`` and ``FORMAL_VERIFICAITON`` because now ``write_testbench`` command can be called many times to generate different versions
|
2021-06-29 14:26:33 -06:00 |
|
tangxifan
|
a3208b332b
|
[Tool] Use 'force' in preconfigured testbenches to avoid instrusive code modification on flip-flop HDL
|
2021-06-29 11:50:53 -06:00 |
|
tangxifan
|
dfe1db996a
|
[Tool] Remove the hardcoded factor when computing simulation timing; There should be no hidden parameters impacting simulation time
|
2021-06-29 09:56:04 -06:00 |
|
tangxifan
|
87446a14c3
|
[Tool] Bug fix for the option ``--embed_bitstream none``
|
2021-06-27 19:45:06 -06:00 |
|
tangxifan
|
90163fab6c
|
[Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>'
|
2021-06-25 15:06:07 -06:00 |
|
tangxifan
|
2bb514c51a
|
[Tool] Support time unit in writing simulation information file
|
2021-06-25 10:33:29 -06:00 |
|
tangxifan
|
bcc16d732c
|
[Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches
|
2021-06-25 10:10:16 -06:00 |
|
tangxifan
|
67dec810eb
|
[Tool] Remove icarus simulator flag; Reduce the file size of preconfigured fabric wrapper by only output the necessary force/deposit HDL codes
|
2021-06-24 17:27:32 -06:00 |
|
tangxifan
|
549657e1fb
|
[Tool] Remove out-of-date flag: INITIAL_SIMULATION from code base
|
2021-06-24 17:13:36 -06:00 |
|
tangxifan
|
21d1519658
|
[Tool] Remove signal initialization flag; Now the HDL codes will not be outputted unless specified in the option
|
2021-06-24 16:56:28 -06:00 |
|
tangxifan
|
fed975c52a
|
[Tool] Add postfix removal support in write_io_mapping command
|
2021-06-18 16:13:50 -06:00 |
|
tangxifan
|
d9d57aad42
|
[Tool] Added default net type options to verilog testbench generator command
|
2021-06-14 11:37:49 -06:00 |
|
tangxifan
|
7ade48343c
|
[Tool] Deprecate command 'write_verilog_testbench'
|
2021-06-09 17:06:01 -06:00 |
|
tangxifan
|
97396eda2b
|
[Tool] Add a new command 'write_simulation_task_info'
|
2021-06-08 22:10:02 -06:00 |
|
tangxifan
|
d2275b971d
|
[Tool] Add a new command 'write_preconfigured_testbench'
|
2021-06-08 21:53:51 -06:00 |
|
tangxifan
|
85679c0fe2
|
[Tool] Bug fix in the top testbench switch due to fast configuration
|
2021-06-08 21:32:26 -06:00 |
|
tangxifan
|
8db19c7af9
|
[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
|
2021-06-08 21:28:16 -06:00 |
|
tangxifan
|
5075c68418
|
[Tool] Remove duplicated codes on fast configuration
|
2021-06-08 20:58:04 -06:00 |
|
tangxifan
|
4aef9d5c96
|
[Tool] Remove redundant codes
|
2021-06-07 21:54:01 -06:00 |
|
tangxifan
|
366dcff75d
|
[Tool] Now 'write_full_testbench' supports flatten(vanilla) configuration protocol
|
2021-06-07 21:49:31 -06:00 |
|
tangxifan
|
9808b61b36
|
[Tool] Bug fix on the unfit vector size of bit index register in Verilog testbench in some cases
|
2021-06-07 20:06:39 -06:00 |
|
tangxifan
|
ba75c18378
|
[Tool] Now 'write_full_testbench' supports memory bank configuration protocol
|
2021-06-07 17:40:07 -06:00 |
|
tangxifan
|
1a5902ca74
|
[Tool] Bug fix in finding pruned bitstream for frame-based protocol when fast configuration is enabled
|
2021-06-07 14:32:56 -06:00 |
|
tangxifan
|
af298de121
|
[Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol
|
2021-06-07 13:53:32 -06:00 |
|
tangxifan
|
d644b8f22d
|
[Tool] Support external bitstream file when generating full testbench for frame-based decoder
|
2021-06-07 11:55:11 -06:00 |
|
tangxifan
|
d98be9f87b
|
[Tool] Remove icarus requirement on vcd writing in Verilog testbenches; Since vcd writing commands are standard Verilog
|
2021-06-04 16:45:00 -06:00 |
|
tangxifan
|
6e69c2d70a
|
[Tool] Patch fast configuration in full Verilog testbench generator
|
2021-06-04 16:34:55 -06:00 |
|
tangxifan
|
98308133c1
|
[Tool] Add configuration skip capability to top testbench which loads external bitstream file
|
2021-06-04 11:24:05 -06:00 |
|
tangxifan
|
adb18d28b8
|
[Tool] Remove unused arguments
|
2021-06-04 10:37:28 -06:00 |
|
tangxifan
|
ae6a46cd60
|
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
|
2021-06-03 15:41:11 -06:00 |
|
tangxifan
|
0b49c22682
|
[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
|
2021-04-18 16:11:11 -06:00 |
|
tangxifan
|
6550ea3dfa
|
[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
|
2021-04-18 12:02:49 -06:00 |
|
tangxifan
|
6e9b24f9bf
|
[Tool] Patch the invalid pin constraint net name
|
2021-04-17 19:56:30 -06:00 |
|
tangxifan
|
253422e7b7
|
[Tool] Bugfix due to refactoring
|
2021-04-17 19:27:03 -06:00 |
|
tangxifan
|
02ca51d84b
|
[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes
|
2021-04-17 17:45:50 -06:00 |
|
tangxifan
|
d95a1e2776
|
[Tool] Encapulate search function in PinConstraint data structure
|
2021-04-17 17:31:55 -06:00 |
|
tangxifan
|
da619fabe7
|
[Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench
|
2021-04-17 17:19:34 -06:00 |
|
tangxifan
|
6e1b58f8a6
|
[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports
|
2021-04-17 15:05:22 -06:00 |
|
tangxifan
|
4b8f5f294a
|
[Tool] Capsulate fabric bitstream organization for configuration chain
|
2021-04-10 14:28:31 -06:00 |
|
tangxifan
|
afa0e751da
|
[Tool] Use alias for complex bitstream data types
|
2021-04-10 14:12:02 -06:00 |
|
tangxifan
|
fa11410425
|
[Tool] Remove exceptions on outputing verilog port with lsb=0
|
2021-03-17 20:27:08 -06:00 |
|
tangxifan
|
521e1850c8
|
[Tool] Correct syntax errors for timing definition in verilog for iverilog 10.1
|
2021-02-28 17:04:27 -07:00 |
|
tangxifan
|
73461971d2
|
[Tool] Bug fix for printing single-bit ports in Verilog netlists
|
2021-02-28 16:12:57 -07:00 |
|
tangxifan
|
15e26a5602
|
[Tool] Support default_net_type Verilog syntex in fabric generator
|
2021-02-28 11:57:40 -07:00 |
|
tangxifan
|
d2defebee9
|
[Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
|
2021-01-22 16:42:13 -07:00 |
|
tangxifan
|
3f80a26172
|
[Tool] Bug fix for combinational benchmarks in pre-config testbench generation
|
2021-01-19 18:22:50 -07:00 |