tangxifan
|
6607bb7e48
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[core] now fpga verilog supports tile modules
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2023-07-18 22:35:22 -07:00 |
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tangxifan
|
ddfb0c4afd
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[core] now mock fpga top supports fpga core wrapper
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2023-06-26 15:06:11 -07:00 |
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tangxifan
|
83fa6a421e
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[core] code format
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2023-06-26 10:06:17 -07:00 |
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tangxifan
|
70f40cd21a
|
[core] fixing bugs in the preconfig module when supporting dut module of fpga_core
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2023-06-26 10:03:19 -07:00 |
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tangxifan
|
919d6d8608
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[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
|
2023-06-25 22:49:51 -07:00 |
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tangxifan
|
205881d0e7
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[core] fixed the bug when using fpga_core instead of fpga_top
|
2023-06-25 18:03:15 -07:00 |
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tangxifan
|
150653287d
|
[core] supporting io naming for verilog testbench generators
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2023-06-25 15:29:27 -07:00 |
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tangxifan
|
bdda695cc0
|
[core] format
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2023-06-18 21:18:35 -07:00 |
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tangxifan
|
cef573529d
|
[core] now fpga verilog can output fpga core netlist
|
2023-06-18 21:17:50 -07:00 |
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tangxifan
|
b6c90eb99a
|
[core] fixed several bugs which causes bgf and pcf support in mock wrapper failed
|
2023-05-27 12:13:16 -07:00 |
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tangxifan
|
e1feebc96d
|
[core] fixing bugs on pcf and bgf support for mock efpga wrapper
|
2023-05-26 21:54:08 -07:00 |
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tangxifan
|
0abc5af1a9
|
[core] fixed the bug supporting global nets
|
2023-05-26 20:44:04 -07:00 |
|
tangxifan
|
a9e5e1af89
|
[core] now fabric netlist include mock wrapper
|
2023-05-26 18:49:57 -07:00 |
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tangxifan
|
788b1495dd
|
[core] split a big function to 4 sub functions so that we can efficiently reuse for mock wrapper
|
2023-05-26 17:31:07 -07:00 |
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tangxifan
|
f7afbfa0bd
|
[core] fixed some bugs
|
2023-05-26 12:26:30 -07:00 |
|
tangxifan
|
e9848c5728
|
[core] typo
|
2023-05-26 10:24:21 -07:00 |
|
tangxifan
|
45e25e4152
|
[core] hooking up API with command
|
2023-05-25 19:50:39 -07:00 |
|
tangxifan
|
affe5c5d1e
|
[core] developing mock wrapper generator
|
2023-05-25 18:50:47 -07:00 |
|
tangxifan
|
e11e4dc3f4
|
[core] comment on current limitations
|
2023-04-24 14:59:43 +08:00 |
|
tangxifan
|
d9af8dd722
|
[core] did some dirty fix but now dv should pass. Not sure why usig a shorter bitstream does not work
|
2023-04-24 14:50:42 +08:00 |
|
tangxifan
|
679c6e9b43
|
[core] debugging
|
2023-04-24 14:05:51 +08:00 |
|
tangxifan
|
3c6a4d34d8
|
[core] code format
|
2023-04-24 13:36:59 +08:00 |
|
tangxifan
|
715765d81b
|
[core] code complete for top testbench generator on ccffv2 upgrades
|
2023-04-24 13:34:44 +08:00 |
|
tangxifan
|
667d9df028
|
[core] developing testbench generator for ccff v2
|
2023-04-24 11:36:21 +08:00 |
|
tangxifan
|
f00acf1e62
|
[code] fixed all the compiler warnings under openfpga/src
|
2023-01-31 12:51:52 -08:00 |
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tangxifan
|
e2debd2dde
|
[engine] add missing header files after coding formatter sorts the include files
|
2022-10-06 18:08:57 -07:00 |
|
tangxifan
|
6d31b319a2
|
[engine] update source files subject to code formatting rules
|
2022-10-06 17:08:50 -07:00 |
|
tangxifan
|
dfe30df462
|
[engine] resolve compilation warnings
|
2022-08-17 16:32:21 -07:00 |
|
tangxifan
|
e0ae851e28
|
[engine] correcting compilation errors due to vpr upgrade
|
2022-08-17 16:25:12 -07:00 |
|
tangxifan
|
8ab090651a
|
[FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports
|
2022-03-16 20:51:37 +08:00 |
|
tangxifan
|
235887e03a
|
[FPGA-Verilog] Fixed a bug on config-enable signals
|
2022-02-23 22:35:23 -08:00 |
|
tangxifan
|
086642d134
|
[FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly
|
2022-02-23 15:33:24 -08:00 |
|
tangxifan
|
1c18d14ad5
|
[FPGA-Verilog] Add big/little endian support to output ports
|
2022-02-19 09:23:48 -08:00 |
|
tangxifan
|
3e43a60fdc
|
[FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks
|
2022-02-19 09:15:38 -08:00 |
|
tangxifan
|
671188dfa4
|
[FPGA-Verilog] Now support big/little-endian in bus group
|
2022-02-18 23:05:03 -08:00 |
|
tangxifan
|
790715f46a
|
[FPGA-Verilog] Fixing bugs when using bus group in full testbench generator
|
2022-02-18 15:41:35 -08:00 |
|
tangxifan
|
401f673f16
|
[FPGA-Verilog] Streamline codes by using APIs
|
2022-02-18 14:47:36 -08:00 |
|
tangxifan
|
c16ea8d082
|
[FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches
|
2022-02-18 14:34:32 -08:00 |
|
tangxifan
|
a4dc86a33d
|
[FPGA-Verilog] Now output atom block name removal has a dedicated function
|
2022-02-18 14:30:46 -08:00 |
|
tangxifan
|
f5dd89bbd9
|
[FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used
|
2022-02-18 14:08:03 -08:00 |
|
tangxifan
|
0d620888ab
|
[FPGA-Verilog] Now instance can output bus ports with all the pins
|
2022-02-18 12:03:26 -08:00 |
|
tangxifan
|
aa375fd7a4
|
[FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator
|
2022-02-18 11:31:11 -08:00 |
|
tangxifan
|
6da0ede9b0
|
[FPGA-Verilog] Adding bus group support to all Verilog testbench generators
|
2022-02-17 23:48:44 -08:00 |
|
tangxifan
|
c96f0d199d
|
[FPGA-Verilog] Adding bus group support in Verilog testbenches
|
2022-02-17 23:14:28 -08:00 |
|
tangxifan
|
e67f8ad8b2
|
[FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase
|
2022-02-15 17:19:50 -08:00 |
|
tangxifan
|
be8f18310d
|
[FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances
|
2022-02-14 17:16:26 -08:00 |
|
tangxifan
|
d3f68db228
|
[FPGA-Verilog] fixing bugs in reset ports for counters in full testbenches
|
2022-02-14 17:00:54 -08:00 |
|
tangxifan
|
34e192c5ca
|
[FPGA-Verilog] Fixed a bug on wiring FPGA global ports
|
2022-02-14 15:21:29 -08:00 |
|
tangxifan
|
8d48492ec0
|
[FPGA-Verilog] Add clock ports to the white list when adding postfix
|
2022-02-14 11:09:00 -08:00 |
|
tangxifan
|
5794561f7b
|
[FPGA-Verilog] Now shared input wire/register has a postfix in full testbench
|
2022-02-14 10:39:27 -08:00 |