9641aaf6c4
Update test
2024-07-26 02:17:25 -07:00
2ef362d53d
Init support overwriting bitstream
2024-07-25 17:40:46 -07:00
e614ca7380
[test] use new syntax
2024-07-10 15:03:27 -07:00
977283dd34
[core] typo
2024-07-10 14:12:49 -07:00
af996e563e
[test] add a new test to validate reset generated by internal driver through programmable clock network
2024-07-10 14:11:06 -07:00
b6ff69faac
[test] reworking the testcase to validate clock network with internal drivers
2024-07-10 11:36:22 -07:00
dbe8e63f53
[test] remove unused files
2024-07-10 10:15:47 -07:00
77304164f4
[test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W
2024-07-10 10:13:41 -07:00
191a3d1c5e
[test] update W
2024-07-10 10:01:31 -07:00
81fe722d98
[test] adjust W
2024-07-09 23:49:01 -07:00
63f2a07c86
[test] typo
2024-07-09 22:54:33 -07:00
a16b3df063
[test] update arch to allow clock access on CLB inputs
2024-07-09 20:59:44 -07:00
43dbeafd44
[test] typo
2024-07-09 20:27:28 -07:00
9ce4b57363
[test] typo
2024-07-09 20:25:39 -07:00
e5d146a67a
[test] add new tests to validate rst on lut and clk on lut features
2024-07-09 20:24:23 -07:00
89e6a0483f
[test] add a new benchmark to validate rst and clk on LUTs
2024-07-09 18:45:33 -07:00
38bb5aa906
[test] add a new benchmark to validate clock on LUT
2024-07-09 18:42:39 -07:00
5efc9d0e00
[test] update golden outputs
2024-07-08 23:24:16 -07:00
5cb104a5f6
[test] fixed a bug
2024-07-08 22:04:40 -07:00
41839bfd7a
[test] typo
2024-07-08 20:21:40 -07:00
03c1c6f917
[test] code format
2024-07-08 18:35:23 -07:00
c7d6c3ab61
[arch] now all the outputs of I/O can only on 1 side
2024-07-08 18:34:13 -07:00
ad053cddca
[test] code format
2024-07-08 18:02:30 -07:00
c30eafac9f
[test] fixed a bug on clk ntwk arch where some io clocks are not tapped
2024-07-08 15:26:16 -07:00
b50acacfba
[test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles
2024-07-08 15:09:31 -07:00
6492d43a01
[test] add a new test to validate perimeter cb using global tile clock
2024-07-08 11:29:20 -07:00
48ae3691c4
[test] typo
2024-07-08 10:57:54 -07:00
5c9c4d93c5
[core] typo
2024-07-08 10:46:47 -07:00
ff56139a53
[test] debugging
2024-07-07 23:07:51 -07:00
b0851a6299
[test] debugging
2024-07-07 23:05:37 -07:00
686cd761b7
[test] debugging
2024-07-07 22:48:21 -07:00
57a378ae59
[test] typo
2024-07-07 22:35:14 -07:00
f784e58383
[test] typo
2024-07-07 22:33:45 -07:00
1a5e2392fc
[test] add a new testcase to validate clock network when perimeter cb is on
2024-07-07 22:32:13 -07:00
db12532eb8
[test] typo
2024-07-07 21:41:39 -07:00
439de61fd0
[test] fixed a bug on ecb support
2024-07-07 14:00:11 -07:00
201b2555e5
[test] code format
2024-07-06 12:15:08 -07:00
43ca3ec747
[test] make arch pin loc for spread for perimeter cb validation
2024-07-06 12:11:31 -07:00
a46820b7c1
[core] add a new test for bottom-left tile grouping
2024-07-05 18:00:37 -07:00
fe73e03c69
[test] changing arch
2024-07-04 21:31:43 -07:00
4064c29d49
[test] updating arch for perimeter cb
2024-07-04 21:23:15 -07:00
5865aebf93
[test] add new arch
2024-07-04 21:12:26 -07:00
a78fddc3cb
[test] add a new testcase to validate perimeter cb
2024-07-03 19:59:24 -07:00
078fad1e74
[test] typo
2024-07-02 14:57:24 -07:00
7e461b09f8
[core] add missing file
2024-07-02 13:22:41 -07:00
1e7cca8ceb
[arch] code format
2024-07-02 11:52:30 -07:00
29452a7442
[test] fixed a bug on out-of-date arch
2024-07-02 11:52:19 -07:00
9b5df76fd5
[test] fix a bug in arch
2024-07-02 09:33:16 -07:00
e00312d29e
[test] typo
2024-07-01 20:34:37 -07:00
1bfcf7574c
[test] validate region and single syntax
2024-07-01 20:33:28 -07:00
28e3cb799e
[test] update 2-clock arch and pcf
2024-06-29 17:40:20 -07:00
12c9686c27
[test] fixed some bugs on arch
2024-06-29 17:38:34 -07:00
5dd0549aed
[core] typo
2024-06-29 17:17:54 -07:00
bc2f02866d
[test] update testcase for 2-clk on programmable clock network
2024-06-29 17:17:05 -07:00
286df30947
[test] update clock arch xml syntax
2024-06-29 11:02:17 -07:00
67554cb8d8
[test] now use correct pcf for clock network testcases
2024-06-29 10:04:03 -07:00
8bc37080fa
[core] debuggging
2024-06-28 23:06:21 -07:00
1c69365938
[core] debugging
2024-06-28 18:17:38 -07:00
f4dd222c47
[test] deploy new testcases to basic reg tests
2024-06-28 13:45:36 -07:00
f1a4304ee7
[test] add new testcases for validate clock tree disable functions
2024-06-28 13:43:53 -07:00
ad5795bece
[test] add extra options to route clock rr_graph command in examples
2024-06-28 13:39:41 -07:00
cab649893b
[core] update clock architecture
2024-06-26 18:06:39 -07:00
c99178f350
[test] fixed a bug on pin locations
2024-06-25 12:34:52 -07:00
2cbb04b90d
[test] add a new testcase to validate programmable clock network with internal drivers
2024-06-25 11:58:05 -07:00
9bb076d892
[test] fixed a bug on pin mapping of tetbenche
2024-06-21 20:29:21 -07:00
292f4a9273
[test] fixed a bug where ace is no required
2024-06-21 18:43:25 -07:00
c2e759fa70
[arch] fixed some bugs
2024-06-21 18:42:29 -07:00
7d67b9d5b9
[test] deploy new tests to basic reg tests
2024-06-21 18:14:54 -07:00
8d7dba2d57
[test] add a new testcase to programmable clock network on supporting reset signals
2024-06-21 18:13:37 -07:00
6c5988575c
[test] update clock network testcase
2024-06-21 16:59:21 -07:00
4d9aacdf8f
[test] add and deploy new benchmark
2024-06-02 14:27:02 -07:00
ad2d101554
[test] deploy new benchmarks
2024-06-02 14:23:08 -07:00
8f2974d7a1
[test] update golden copies
2024-05-29 10:31:19 -07:00
3c49af6a08
[test] code format
2024-05-20 21:28:46 -07:00
f25081eb31
[test] add a new test to validate ecb when tile modules are used
2024-05-20 21:10:49 -07:00
852b01aaff
[test] rework
2024-05-20 17:20:04 -07:00
a9a5fbee34
[test] add fully connected feedback connections to directlist
2024-05-20 17:02:20 -07:00
807c37d3ff
[test] fixed some bugs
2024-05-20 13:47:22 -07:00
6146d0be9f
[arch] Move clb I to right side as left side is not supported yet
2024-05-20 13:43:04 -07:00
65dd342c60
[arch] typo
2024-05-20 12:11:22 -07:00
653521755b
[test] add new testcase for ecb to basic regtest
2024-05-20 12:09:12 -07:00
bdc13e491e
[arch] adding openfpga arch for ecb
2024-05-20 12:04:52 -07:00
c795dd2f1a
[arch] adding a new arch where feedback loops are modelled by direct connections
2024-05-20 12:00:39 -07:00
65a8db4f38
[arch] replace out-of-date keywords
2024-05-20 11:18:46 -07:00
372e386330
[test] add new tests to verify rr graph preloading in two file formats
2024-05-09 23:10:45 -07:00
b8b8fb6d3b
[test] update golden files
2024-05-07 13:25:23 -07:00
81730da7b2
[test] update golden files
2024-05-07 13:25:04 -07:00
e72d71fe28
[test] update golden outputs
2024-05-07 13:24:45 -07:00
deee75f828
[test] use a different W to avoid vvp collapse
2024-05-07 12:20:58 -07:00
7a0cd764d3
[test] fixed some bugs
2024-05-07 11:23:33 -07:00
13f8dd096e
[test] create a new example script for fixed routing W case
2024-05-07 10:24:15 -07:00
00f39d55ab
[test] now use fixed routing channel width
2024-05-06 23:32:27 -07:00
3615bdceeb
[test] avoid no-fanin errors for hetero arch
2024-05-06 15:32:27 -07:00
10470b311d
[test] now use latest python3 of ubuntu 22.04
2024-05-06 11:44:45 -07:00
c334a0a792
[test] fixed a bug and add golden outputs
2024-05-02 22:07:22 -07:00
98006608c2
[test] add fabric hierarchy file to golden outputs
2024-05-02 22:03:23 -07:00
4e3bbbe45e
[test] add options to write fabric hierarchy file
2024-05-02 22:00:47 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
1af8a4ae4f
[test] add golden outputs
2024-04-11 15:20:34 -07:00
9b0a491819
[test] now validate no time stamp file for fabric pin physical location
2024-04-11 15:16:34 -07:00
chungshien-chai
tangxifan
chungshien