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[test] fixed a bug on pin locations

This commit is contained in:
tangxifan 2024-06-25 12:34:52 -07:00
parent 4640e74e7e
commit c99178f350
1 changed files with 6 additions and 1 deletions
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7
openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
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@ -107,7 +107,12 @@
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="spread"/>
<pinlocations pattern="custom">
<loc side="left"></loc>
<loc side="top"></loc>
<loc side="right">clb.reset clb.clk clb.O[4:7] clb.I[6:11]</loc>
<loc side="bottom">clb.O[0:3] clb.I[0:5]</loc>
</pinlocations>
</sub_tile>
</tile>
</tiles>