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[test] fixed a bug on out-of-date arch

This commit is contained in:
tangxifan 2024-07-02 11:52:19 -07:00
parent 9b5df76fd5
commit 29452a7442
1 changed files with 3 additions and 3 deletions
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6
openfpga_flow/tasks/basic_tests/tile_organization/homo_fabric_tile_clkntwk/config/clk_arch_1clk_2layer.xml
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@ -1,5 +1,5 @@
<clock_networks default_segment="L1" default_switch="ipin_cblock">
<clock_network name="clk_tree_2lvl" width="1">
<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
<clock_network name="clk_tree_2lvl" global_port="clk[0:0]">
<spine name="spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
<switch_point tap="rib_lvl1_sw0_upper" x="1" y="1"/>
<switch_point tap="rib_lvl1_sw0_lower" x="1" y="1"/>
@ -11,7 +11,7 @@
<spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<tap tile_pin="clb[0:0].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
</taps>
</clock_network>
</clock_networks>