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[test] update 2-clock arch and pcf

This commit is contained in:
tangxifan 2024-06-29 17:40:20 -07:00
parent 12c9686c27
commit 28e3cb799e
4 changed files with 2 additions and 4 deletions
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2
openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/clk_arch_2clk_2layer.xml
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@ -12,7 +12,7 @@
<spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
<all from_pin="clk[1:1]" to_pin="clb[0:0].clk[1:1]"/>
<all from_pin="clk[1:1]" to_pin="clb[0:0].clk[0:0]"/>
</taps>
</clock_network>
</clock_networks>

1
openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused/config/repack_constraints.xml
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@ -1,5 +1,4 @@
<repack_design_constraints>
<pin_constraint pb_type="clb" pin="clk[0:0]" net="clk"/>
<pin_constraint pb_type="clb" pin="clk[1:1]" net="OPEN"/>
</repack_design_constraints>

2
openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/clk_arch_2clk_2layer.xml
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@ -12,7 +12,7 @@
<spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
<all from_pin="clk[1:1]" to_pin="clb[0:0].clk[1:1]"/>
<all from_pin="clk[1:1]" to_pin="clb[0:0].clk[0:0]"/>
</taps>
</clock_network>
</clock_networks>

1
openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree/config/repack_constraints.xml
View File

@ -1,5 +1,4 @@
<repack_design_constraints>
<pin_constraint pb_type="clb" pin="clk[0:0]" net="clk"/>
<pin_constraint pb_type="clb" pin="clk[1:1]" net="OPEN"/>
</repack_design_constraints>