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[test] add extra options to route clock rr_graph command in examples

This commit is contained in:
tangxifan 2024-06-28 13:39:41 -07:00
parent 1094af9f73
commit ad5795bece
8 changed files with 8 additions and 3 deletions
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2
openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga
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@ -22,7 +22,7 @@ append_clock_rr_graph
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Route clock based on clock network definition
route_clock_rr_graph
route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS}
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

2
openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
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@ -22,7 +22,7 @@ append_clock_rr_graph
link_openfpga_arch --sort_gsb_chan_node_in_edges
# Route clock based on clock network definition
route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

2
openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
View File

@ -22,7 +22,7 @@ append_clock_rr_graph
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
# Route clock based on clock network definition
route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

1
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf
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@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml
openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
openfpga_route_clock_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml

1
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf
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@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=40
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml
openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
openfpga_route_clock_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml

1
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf
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@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=24
openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/dummy_repack_constraints.xml
openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/dummy_pin_constraints.xml
openfpga_route_clock_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml

1
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf
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@ -22,6 +22,7 @@ openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=24
openfpga_route_clock_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml

1
openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf
View File

@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=24
openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_constraints.xml
openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml
openfpga_route_clock_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml