diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga
index 92cd639ca..24821bc91 100644
--- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_full_tb_script.openfpga
@@ -22,7 +22,7 @@ append_clock_rr_graph
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
 
 # Route clock based on clock network definition
-route_clock_rr_graph
+route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS}
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
index f62d62ecc..f48be422f 100644
--- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
@@ -22,7 +22,7 @@ append_clock_rr_graph
 link_openfpga_arch --sort_gsb_chan_node_in_edges
 
 # Route clock based on clock network definition
-route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
+route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
index 83cc44860..4d9b21770 100644
--- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
@@ -22,7 +22,7 @@ append_clock_rr_graph
 link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
 
 # Route clock based on clock network definition
-route_clock_rr_graph --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
+route_clock_rr_graph ${OPENFPGA_ROUTE_CLOCK_OPTIONS} --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} 
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf
index d47ef31c7..e6204e15a 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer/config/task.conf
@@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2
 openfpga_vpr_route_chan_width=40
 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer.xml
 openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
+openfpga_route_clock_options=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf
index 6bc568fb0..a88b6c9b1 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf
@@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2
 openfpga_vpr_route_chan_width=40
 openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml
 openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
+openfpga_route_clock_options=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf
index b05af260f..295943e3e 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer/config/task.conf
@@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2
 openfpga_vpr_route_chan_width=24
 openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/dummy_repack_constraints.xml
 openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/dummy_pin_constraints.xml
+openfpga_route_clock_options=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf
index ef0ce93fd..f42445c51 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_2layer_full_tb/config/task.conf
@@ -22,6 +22,7 @@ openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 openfpga_vpr_device_layout=2x2
 openfpga_vpr_route_chan_width=24
+openfpga_route_clock_options=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk1clk2lvl_40nm.xml
diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf
index 190ff11e0..d75606c31 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/task.conf
@@ -24,6 +24,7 @@ openfpga_vpr_device_layout=2x2
 openfpga_vpr_route_chan_width=24
 openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_constraints.xml
 openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints.xml
+openfpga_route_clock_options=
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_Ntwk2clk2lvl_40nm.xml