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[test] deploy new benchmarks

This commit is contained in:
tangxifan 2024-06-02 14:23:08 -07:00
parent ad8ad25250
commit ad2d101554
4 changed files with 42 additions and 1 deletions
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35
openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_4bit/rst_on_lut_4bit.v Normal file
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@ -0,0 +1,35 @@
/////////////////////////////////////////
// Functionality: 4-bit version of A register driven by a combinational logic with reset signal
// Author: Xifan Tang
////////////////////////////////////////
`timescale 1ns / 1ps
module rst_on_lut_4bit(a, b0, b1, b2, b3, q, out0, out1, out2, out3, clk, rst);
input wire rst;
input wire clk;
input wire a;
input wire b0;
input wire b1;
input wire b2;
input wire b3;
output reg q;
output wire out0;
output wire out1;
output wire out2;
output wire out3;
always @(posedge rst or posedge clk) begin
if (rst) begin
q <= 0;
end else begin
q <= a;
end
end
assign out0 = b0 & ~rst;
assign out1 = b1 & ~rst;
assign out2 = b2 & ~rst;
assign out3 = b3 & ~rst;
endmodule

1
openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh
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@ -28,6 +28,7 @@ run-task fpga_bitstream/load_external_architecture_bitstream $@
echo -e "Testing repacker capability in identifying wire LUTs";
run-task fpga_bitstream/repack_wire_lut $@
run-task fpga_bitstream/repack_wire_lut_strong $@
run-task fpga_bitstream/repack_ignore_nets $@
echo -e "Testing overloading default paths for programmable interconnect when generating bitstream";
run-task fpga_bitstream/overload_mux_default_path $@

2
openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/rst_on_lut_repack_dc.xml
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@ -2,7 +2,7 @@
<pin_constraint pb_type="clb" pin="clk[0]" net="clk"/>
<pin_constraint pb_type="clb" pin="reset[0]" net="rst"/>
<ignore_net name="rst" pin="clb.I[0:11]"/>
<reset />
<!-- reset / -->
<!-- Leave lreset unconstrained as it may be mapped to any internal reset signals -->
</repack_design_constraints>

5
openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/task.conf
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@ -28,6 +28,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_lo
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/two_dff_inv_rst/two_dff_inv_rst.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut/rst_on_lut.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_on_lut_4bit/rst_on_lut_4bit.v
[SYNTHESIS_PARAM]
# Yosys script parameters
@ -45,6 +46,10 @@ bench1_top = rst_on_lut
bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml
bench1_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml
bench2_top = rst_on_lut_4bit
bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/rst_on_lut_pc.xml
bench2_openfpga_repack_design_constraint_file=${PATH:TASK_DIR}/config/rst_on_lut_repack_dc.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=