[test] update golden files

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v

@@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb;
 	initial begin
 		clk[0] <= 1'b0;
 		while(1) begin
-			#0.4628907144
+			#0.4880859554
 			clk[0] <= !clk[0];
 		end
 	end
@@ -106,7 +106,7 @@ initial begin
 	$timeformat(-9, 2, "ns", 20);
 	$display("Simulation start");
 // ----- Can be changed by the user for his/her need -------
-	#6.480470181
+	#6.833203316
 	if(nb_error == 0) begin
 		$display("Simulation Succeed");
 	end else begin

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc

@@ -9,14 +9,14 @@
 ##################################################
 # Create clock                                    
 ##################################################
-create_clock clk[0] -period 9.25781396e-10 -waveform {0 4.62890698e-10}
+create_clock clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10}
 
 ##################################################
 # Create input and output delays for used I/Os    
 ##################################################
-set_input_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[11]
-set_input_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[14]
-set_output_delay -clock clk[0] -max 9.25781396e-10 gfpga_pad_GPIO_PAD[1]
+set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[11]
+set_input_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[14]
+set_output_delay -clock clk[0] -max 9.761719211e-10 gfpga_pad_GPIO_PAD[1]
 
 ##################################################
 # Disable timing for unused I/Os    

openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc

@@ -14,7 +14,7 @@ set_units -time s
 ##################################################
 # Create clock                                    
 ##################################################
-create_clock -name clk[0] -period 9.25781396e-10 -waveform {0 4.62890698e-10} [get_ports {clk[0]}]
+create_clock -name clk[0] -period 9.761719211e-10 -waveform {0 4.880859605e-10} [get_ports {clk[0]}]
 ##################################################
 # Create programmable clock                       
 ##################################################

openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v

@@ -47,7 +47,7 @@ module and2_top_formal_verification_random_tb;
 	initial begin
 		clk[0] <= 1'b0;
 		while(1) begin
-			#0.6573184729
+			#0.8625563979
 			clk[0] <= !clk[0];
 		end
 	end
@@ -106,7 +106,7 @@ initial begin
 	$timeformat(-9, 2, "ns", 20);
 	$display("Simulation start");
 // ----- Can be changed by the user for his/her need -------
-	#9.202458382
+	#12.07578945
 	if(nb_error == 0) begin
 		$display("Simulation Succeed");
 	end else begin

openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc

@@ -9,14 +9,14 @@
 ##################################################
 # Create clock                                    
 ##################################################
-create_clock clk[0] -period 1.314636955e-09 -waveform {0 6.573184774e-10}
+create_clock clk[0] -period 1.725112719e-09 -waveform {0 8.625563597e-10}
 
 ##################################################
 # Create input and output delays for used I/Os    
 ##################################################
-set_input_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[38]
-set_input_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[58]
-set_output_delay -clock clk[0] -max 1.314636955e-09 gfpga_pad_GPIO_PAD[17]
+set_input_delay -clock clk[0] -max 1.725112719e-09 gfpga_pad_GPIO_PAD[38]
+set_input_delay -clock clk[0] -max 1.725112719e-09 gfpga_pad_GPIO_PAD[58]
+set_output_delay -clock clk[0] -max 1.725112719e-09 gfpga_pad_GPIO_PAD[17]
 
 ##################################################
 # Disable timing for unused I/Os    

openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/global_ports.sdc

@@ -14,7 +14,7 @@ set_units -time s
 ##################################################
 # Create clock                                    
 ##################################################
-create_clock -name clk[0] -period 1.314636955e-09 -waveform {0 6.573184774e-10} [get_ports {clk[0]}]
+create_clock -name clk[0] -period 1.725112719e-09 -waveform {0 8.625563597e-10} [get_ports {clk[0]}]
 ##################################################
 # Create programmable clock                       
 ##################################################