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[test] rework

This commit is contained in:
tangxifan 2024-05-20 17:20:04 -07:00
parent d3d29a507f
commit 852b01aaff
2 changed files with 3 additions and 3 deletions
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2
openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf
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@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
openfpga_vpr_device_layout=2x2
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzTr_40nm.xml
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif

4
openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzTr_40nm.xml → openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml
View File

@ -65,10 +65,10 @@
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
<pinlocations pattern="custom">
<loc side="top">clb.clk clb.I0[0:3] clb.I1[0:3] clb.O[0:1]</loc>
<loc side="top">clb.clk</loc>
<loc side="right">clb.I2[0:3] clb.I3[0:3] clb.O[2:3]</loc>
<loc side="left"/>
<loc side="bottom"/>
<loc side="bottom">clb.I0[0:3] clb.I1[0:3] clb.O[0:1]</loc>
</pinlocations>
</sub_tile>
</tile>