From 852b01aafff7f3bf2345c1492fd8fbf67c0569a9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 20 May 2024 17:20:04 -0700
Subject: [PATCH] [test] rework

---
 .../tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf     | 2 +-
 ...OrgzTr_40nm.xml => k4_N4_ecb_tileable_TileOrgzBr_40nm.xml} | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
 rename openfpga_flow/vpr_arch/{k4_N4_ecb_tileable_TileOrgzTr_40nm.xml => k4_N4_ecb_tileable_TileOrgzBr_40nm.xml} (99%)

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf
index 6a864a50c..87f77596d 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_ecb/config/task.conf
@@ -22,7 +22,7 @@ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulatio
 openfpga_vpr_device_layout=2x2
 
 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzTr_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
diff --git a/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzTr_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml
similarity index 99%
rename from openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzTr_40nm.xml
rename to openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml
index 59fd77084..4597207bb 100644
--- a/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzTr_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_ecb_tileable_TileOrgzBr_40nm.xml
@@ -65,10 +65,10 @@
         <clock name="clk" num_pins="1"/>
         <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
         <pinlocations pattern="custom">
-          <loc side="top">clb.clk clb.I0[0:3] clb.I1[0:3] clb.O[0:1]</loc>
+          <loc side="top">clb.clk</loc>
           <loc side="right">clb.I2[0:3] clb.I3[0:3] clb.O[2:3]</loc>
           <loc side="left"/>
-          <loc side="bottom"/>
+          <loc side="bottom">clb.I0[0:3] clb.I1[0:3] clb.O[0:1]</loc>
         </pinlocations>
       </sub_tile>
     </tile>