Clifford Wolf
014a41fcf3
Implemented recursive techmap
2014-08-03 12:40:43 +02:00
Clifford Wolf
08ec33a5e5
Implemented simplemap support for "techmap -extern"
2014-08-02 21:55:13 +02:00
Clifford Wolf
b6acbc82e6
Bugfix in "techmap -extern"
2014-08-02 20:54:30 +02:00
Clifford Wolf
04727c7e0f
No implicit conversion from IdString to anything else
2014-08-02 18:58:40 +02:00
Clifford Wolf
768eb846c4
More bugfixes related to new RTLIL::IdString
2014-08-02 18:14:21 +02:00
Clifford Wolf
b9bd22b8c8
More cleanups related to RTLIL::IdString usage
2014-08-02 13:19:57 +02:00
Clifford Wolf
bd74ed7da4
Replaced sha1 implementation
2014-08-01 19:01:10 +02:00
Clifford Wolf
cdae8abe16
Renamed port access function on RTLIL::Cell, added param access functions
2014-07-31 16:38:54 +02:00
Clifford Wolf
e6d33513a5
Added module->design and cell->module, wire->module pointers
2014-07-31 14:11:39 +02:00
Clifford Wolf
1cb25c05b3
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
2014-07-31 13:19:47 +02:00
Clifford Wolf
1202f7aa4b
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
Clifford Wolf
6ca0c569d9
Added "techmap -assert"
2014-07-31 02:21:41 +02:00
Clifford Wolf
2541489105
Added techmap CONSTMAP feature
2014-07-30 22:04:30 +02:00
Clifford Wolf
03c96f9ce7
Added "techmap -map %{design-name}"
2014-07-29 16:35:13 +02:00
Clifford Wolf
7bd2d1064f
Using log_assert() instead of assert()
2014-07-28 11:27:48 +02:00
Clifford Wolf
8b0f50792c
Added techmap -extern
2014-07-27 21:31:18 +02:00
Clifford Wolf
5da343b7de
Added topological sorting to techmap
2014-07-27 16:43:39 +02:00
Clifford Wolf
49f72421d5
Using new obj iterator API in a few places
2014-07-27 11:32:42 +02:00
Clifford Wolf
10e5791c5e
Refactoring: Renamed RTLIL::Design::modules to modules_
2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156
Refactoring: Renamed RTLIL::Module::cells to cells_
2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad
Refactoring: Renamed RTLIL::Module::wires to wires_
2014-07-27 01:49:51 +02:00
Clifford Wolf
d68c993ed2
Changed more code to the new RTLIL::Wire constructors
2014-07-26 21:30:38 +02:00
Clifford Wolf
3f4e3ca8ad
More RTLIL::Cell API usage cleanups
2014-07-26 16:14:02 +02:00
Clifford Wolf
f8fdc47d33
Manual fixes for new cell connections API
2014-07-26 15:58:23 +02:00
Clifford Wolf
b7dda72302
Changed users of cell->connections_ to the new API (sed command)
...
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b
Renamed RTLIL::{Module,Cell}::connections to connections_
2014-07-26 11:58:03 +02:00
Clifford Wolf
4755e14e7b
Added copy-constructor-like module->addCell(name, other) method
2014-07-26 00:38:44 +02:00
Clifford Wolf
2bec47a404
Use only module->addCell() and module->remove() to create and delete cells
2014-07-25 17:56:19 +02:00
Clifford Wolf
45b4154b37
Added "make SMALL=1"
2014-07-24 19:03:57 +02:00
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
Clifford Wolf
a62c21c9c6
Removed RTLIL::SigSpec::expand() method
2014-07-23 19:34:51 +02:00
Clifford Wolf
4e802eb7f6
Fixed all users of SigSpec::chunks_rw() and removed it
2014-07-23 15:36:09 +02:00
Clifford Wolf
ec923652e2
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
2014-07-23 09:49:43 +02:00
Clifford Wolf
28b3fd05fa
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f
SigSpec refactoring: using the accessor functions everywhere
2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81
SigSpec refactoring: renamed chunks and width to __chunks and __width
2014-07-22 20:39:37 +02:00
Clifford Wolf
361e0d62ff
Replaced depricated NEW_WIRE macro with module->addWire() calls
2014-07-21 12:42:02 +02:00
Clifford Wolf
1d88f1cf9f
Removed deprecated module->new_wire()
2014-07-21 12:35:06 +02:00
Clifford Wolf
8d04ca7d22
Added call_on_selection() and call_on_module() API
2014-07-20 15:33:06 +02:00
Clifford Wolf
b76bf05cda
Added support for "blackbox" attribute to iopadmap
2014-07-17 08:59:07 +02:00
Clifford Wolf
64a6906cc4
Added support for "blackbox" attribute to flatten/techmap
2014-07-17 08:58:51 +02:00
Johann Glaser
684c85902d
be more verbose when techmap yielded processes
2014-05-26 17:13:41 +02:00
Clifford Wolf
fad8558eb5
Merged OSX fixes from Siesh1oo with some modifications
2014-03-13 12:48:10 +01:00
Siesh1oo
8127d5e8c3
- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname().
...
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
- passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
2014-03-12 23:17:14 +01:00
Clifford Wolf
9087ece97c
OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:52:37 +01:00
Clifford Wolf
91704a7853
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:24:24 +01:00
Clifford Wolf
fcae92868d
Fixed dumping of timing() { .. } block in libparse
2014-03-09 15:16:07 +01:00
Clifford Wolf
1ecaf1bb76
Added techmap -max_iter option
2014-03-06 12:15:17 +01:00
Clifford Wolf
4e43cb7317
Added _TECHMAP_REPLACE_ feature to techmap
2014-02-20 23:42:07 +01:00
Clifford Wolf
737b71c735
Added "extract -ignore_parameters" and "extract -ignore_param ..."
2014-02-20 23:31:13 +01:00
Clifford Wolf
236fc4209c
Added "extract -map %<design_name>"
2014-02-20 23:30:15 +01:00
Clifford Wolf
a71d09421d
Added techmap support for _TECHMAP_CONNMAP_*_
2014-02-18 19:51:00 +01:00
Clifford Wolf
ca53ef5098
Better preserve wires when flattening (in comparison to techmap)
2014-02-17 09:44:39 +01:00
Clifford Wolf
6d63f39eb6
Added some additional checks to techmap
2014-02-16 22:18:06 +01:00
Clifford Wolf
a9b11d7c83
Added CONSTMSK and CONSTVAL feature to techmap
2014-02-16 21:58:59 +01:00
Clifford Wolf
d3dc22a90f
Added recursion support to techmap
2014-02-16 17:16:44 +01:00
Clifford Wolf
623a68f528
Added iopadmap -bits
2014-02-15 21:59:26 +01:00
Clifford Wolf
cdf0f10760
Fixed dfflibmap for cell libraries with no set-reset-ff
2014-02-15 16:34:12 +01:00
Clifford Wolf
6644f80d97
Moved some passes to other source directories
2014-02-08 14:39:15 +01:00
Clifford Wolf
fc3b3c4ec3
Added $slice and $concat cell types
2014-02-07 17:44:57 +01:00
Clifford Wolf
c13c5b9b7b
Changed techmap description from "simple" to "generic"
2014-02-06 13:10:06 +01:00
Clifford Wolf
c1ed2607fb
Added support for // comments in liberty parser
2014-01-25 06:32:16 +01:00
Clifford Wolf
32a91458a7
Added hilomap command
2014-01-19 21:58:58 +01:00
Clifford Wolf
9a00980129
renamed LibertyParer to LibertyParser
2014-01-14 18:57:47 +01:00
Clifford Wolf
c1da7661a5
Added "+" to list of liberty token characters
2014-01-14 18:56:29 +01:00
Clifford Wolf
bf607df6d5
Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)
2013-12-29 17:39:49 +01:00
Clifford Wolf
fe8ec32a1c
Added new cell types to manual
2013-12-28 12:10:32 +01:00
Clifford Wolf
c69c416d28
Added $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-28 12:02:14 +01:00
Clifford Wolf
334b0cc803
Fixed dfflibmap for unused output ports
2013-12-21 20:47:22 +01:00
Clifford Wolf
8856cec308
Now prefer smallest cells in dfflibmap
2013-12-21 08:42:37 +01:00
Clifford Wolf
1fb29050e5
Cleanup of dfflibmap cellmap exploration code
2013-12-20 14:21:18 +01:00
Clifford Wolf
eaf7d9675d
Further improved dfflibmap cellmap exploration
2013-12-20 12:34:34 +01:00
Clifford Wolf
404bcc2d1e
Fixed dfflibmap endless-loop bug
2013-12-20 12:13:51 +01:00
Clifford Wolf
c904f5e197
Prefer non-inverted clocks in dfflibmap
2013-12-19 13:21:57 +01:00
Clifford Wolf
f4b46ed31e
Replaced signed_parameters API with CONST_FLAG_SIGNED
2013-12-04 14:24:44 +01:00
Clifford Wolf
93a70959f3
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
Clifford Wolf
76f7c10cfc
Using simplemap mappers from techmap
2013-11-24 23:31:14 +01:00
Clifford Wolf
3ee33cbdaf
Added simplemap pass
2013-11-24 22:52:30 +01:00
Clifford Wolf
8dafecd34d
Added module->avail_parameters (for advanced techmap features)
2013-11-24 20:29:07 +01:00
Clifford Wolf
4011d47646
Added techmap -D and -I options
2013-11-24 20:04:48 +01:00
Clifford Wolf
20175afd29
Added "techmap -share_map" option
2013-11-24 19:50:25 +01:00
Clifford Wolf
609caa23b5
Implemented correct handling of signed module parameters
2013-11-24 17:17:21 +01:00
Clifford Wolf
72b35e0b99
Fixed "flatten" top-module detection: Only use on fully selected designs
2013-11-24 14:10:46 +01:00
Clifford Wolf
28093d9dd2
Added "top" attribute to mark top module in hierarchy
2013-11-24 05:03:43 +01:00
Clifford Wolf
5f9c7fc6ea
Improved handling of techmap special wires
2013-11-23 16:49:58 +01:00
Clifford Wolf
532091afcb
Added more generic _TECHMAP_ wire mechanism to techmap pass
2013-11-23 15:58:06 +01:00
Clifford Wolf
295e352ba6
Renamed "placeholder" to "blackbox"
2013-11-22 15:01:12 +01:00
Clifford Wolf
378cc509cd
Call internal checker more often
2013-11-10 23:24:21 +01:00
Clifford Wolf
0efe16f118
Added placeholder check to dfflibmap and cleaned up some other placeholder checks
2013-10-31 12:27:07 +01:00
Clifford Wolf
ceb971eab9
Added support for i/o buffers to iopadmap
2013-10-26 22:27:40 +02:00
Clifford Wolf
dd56004fc0
Added support for sr flip-flops to dfflibmap
2013-10-24 18:20:06 +02:00
Clifford Wolf
e679a5d046
Fixed handling of boolean attributes (passes)
2013-10-24 11:37:54 +02:00
Clifford Wolf
9bc703b964
Improved way of connecting ports in techmap pass
2013-10-17 22:19:38 +02:00
Clifford Wolf
96e7abad48
Added iopadmap pass
2013-10-16 16:16:06 +02:00
Clifford Wolf
b6db2d9b33
Moved dfflibmap from passes/dfflibmap to passes/techmap
2013-10-16 15:32:26 +02:00
Clifford Wolf
288ba9618a
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
Clifford Wolf
376150c926
Added techmap -opt mode
2013-08-09 15:20:22 +02:00
Clifford Wolf
5f2c5f9017
Fixed techmap/flatten for positional module arguments
2013-05-26 12:21:17 +02:00
Clifford Wolf
e04d88cf22
Added missing newline to some error messages
2013-05-23 11:19:33 +02:00
Clifford Wolf
83c743f717
Added support for const cell inputs in techmap
2013-04-27 18:30:29 +02:00
Clifford Wolf
b1cb4d7871
Added "flatten" pass
2013-04-26 14:40:45 +02:00
Clifford Wolf
8edf4f378a
Added proper TECHMAP_FAIL support and added support for the celltype attribute in the map file
2013-03-28 10:12:50 +01:00
Clifford Wolf
020a35d11e
Removed date from auto-generated passes/techmap/stdcells.inc
2013-03-18 07:32:33 +01:00
Johann Glaser
3b8ebd694d
add header to autogenerated file on its origin
2013-03-18 07:28:31 +01:00
Johann Glaser
cd8008bda0
fixed typos
2013-03-18 07:28:31 +01:00
Clifford Wolf
b96ffed69b
Automatically select new objects in abc and techmap passes
2013-03-08 09:16:25 +01:00
Clifford Wolf
7fccad92f7
Added more help messages
2013-03-01 00:36:19 +01:00
Clifford Wolf
6543917fb8
added .gitignore files
2013-01-05 11:19:11 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00