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Author SHA1 Message Date
Kamil Rakoczy de649b9194 Revert "Revert PRs #2203 and #2244." 
This reverts commit 9c120b89ac.
 2020-07-10 09:59:48 +02:00
whitequark 9c120b89ac Revert PRs #2203 and #2244. 
This reverts commit 7e83a51fc9.
This reverts commit b422f2e4d0.
This reverts commit 7cb56f34b0.
This reverts commit 6f9be939bd.
This reverts commit 76a34dc5f3.
 2020-07-09 19:36:32 +00:00
Marcelina Kościelnicka 7ed9d18907 dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
Marcelina Kościelnicka 32d2cc8c28 clkbufmap: improve input pad handling. 
- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
  buffer
 2020-07-09 18:48:01 +02:00
clairexen 802671b22e
Merge pull request #2244 from antmicro/logic 
Add logic type support to parameters
 2020-07-09 18:39:30 +02:00
Marcelina Kościelnicka 03e28f7ab4 clk2fflogic: Consistently treat async control signals as negative hold. 
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
 2020-07-09 18:12:47 +02:00
Marcelina Kościelnicka e9c2c1b717 dfflegalize: Add special support for const-D latches. 
Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q.  Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.
 2020-07-09 18:11:32 +02:00
Marcelina Kościelnicka c73ebeb90e gowin: Use dfflegalize. 2020-07-06 12:27:46 +02:00
Kamil Rakoczy b422f2e4d0 Add logic param and integer bad syntax tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-07-06 09:18:48 +02:00
Dan Ravensloft 09ecb9b2cf intel_alm: direct M10K instantiation 2020-07-05 23:28:59 +02:00
Dan Ravensloft 7f45cab27a synth_gowin: ABC9 support 
This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.
 2020-07-05 22:07:17 +02:00
Dan Ravensloft 0d4c2f0a65 intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
Marcelina Kościelnicka 7afcb72c98 opt_expr: Fix crash on $mul optimization with more zeros removed than Y has. 
Fixes #2221.
 2020-07-05 06:31:58 +02:00
Dan Ravensloft b004f09018 intel_alm: DSP inference 2020-07-05 05:39:20 +02:00
Marcelina Kościelnicka 3ca2de0f77 synth_intel_alm: Use dfflegalize. 2020-07-04 22:56:16 +02:00
Dan Ravensloft c6765443fd Improve MISTRAL_FF specify rules 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2020-07-04 19:45:10 +02:00
Eddie Hung 52fbaeca07 tests: update fsm.ys resource count 
Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862?
 2020-07-04 19:45:10 +02:00
clairexen 5428666151
Merge pull request #2186 from YosysHQ/mwk/dfflegalize 
Add dfflegalize pass.
 2020-07-02 17:46:11 +02:00
clairexen 7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar 
Signed and macro grammar update
 2020-07-01 16:41:32 +02:00
clairexen 8ce4f8790e
Merge pull request #2179 from splhack/static-cast 
Support SystemVerilog Static Cast
 2020-07-01 16:40:20 +02:00
Marcelina Kościelnicka 6b42819a37 dfflegalize: Add tests. 2020-07-01 01:57:15 +02:00
Zachary Snow 27cec16cda Allow constant function calls in for loops and generate if and case 2020-06-29 16:06:17 -06:00
Kamil Rakoczy 76a34dc5f3 Add signed/unsigned tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-26 15:38:20 +02:00
Kamil Rakoczy 39c39848a2 Add sub-assign and and-assign tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 14:32:05 +02:00
Kamil Rakoczy 470df03f3d Move combined assign tests to single file 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-25 14:19:16 +02:00
Kamil Rakoczy f6d06c9f7b Add xor-assignment test 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 14:46:21 +02:00
Kamil Rakoczy a5ca4eeefb Add or-assignment and plus-assignment tests 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-24 11:56:26 +02:00
Marcelina Kościelnicka 88e7f90663 Update dff2dffe, dff2dffs, zinit to new FF types. 2020-06-23 18:24:53 +02:00
Kazuki Sakamoto 6bf75be73b static cast: add tests 2020-06-19 17:40:38 -07:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Dan Ravensloft 8b4eb78849 intel_alm: fix DFFE matching 2020-06-11 19:55:51 +02:00
Claire Wolf b3b515087d Fix tests/opt/opt_rmdff 
This only passed before because "prep" was also running opt_rmdff

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-09 22:48:26 +02:00
Peter Crozier 01ec681373 Support 2D bit arrays in structures. Optimise array indexing. 2020-06-08 20:34:52 +01:00
Peter Crozier 76c499db71 Support packed arrays in struct/union. 2020-06-07 18:33:11 +01:00
Claire Wolf 7112f187cd Add missing .gitignore file 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 22:25:47 +02:00
clairexen 352731df4e
Merge pull request #2041 from PeterCrozier/struct 
Implementation of  SV structs.
 2020-06-04 18:26:07 +02:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
Eddie Hung 45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes 
abc9: fixes around handling combinatorial loops
 2020-06-03 17:35:46 -07:00
Peter Crozier 0d3f7ea011
Merge branch 'master' into struct 2020-06-03 17:19:28 +01:00
Eddie Hung 8a11019d38 tests: tidy up testcase 2020-06-03 08:41:55 -07:00
Eddie Hung 46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings 
tests: reduce test warnings
 2020-06-03 08:37:07 -07:00
Miodrag Milanovic 0a88f002e5 allow range for mux test 2020-06-01 13:48:19 +02:00
Eddie Hung ea4374a223 abc9_ops: update messaging (credit to @Xiretza for spotting) 2020-05-30 08:57:48 -07:00
Eddie Hung d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
clairexen 0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic 
ast/simplify: don't bitblast async ROMs declared as `logic`
 2020-05-29 16:52:11 +02:00
Xiretza 6a2bac21d3
Expand tests/simple/constmuldivmod.v 2020-05-28 22:59:04 +02:00
whitequark abac0ab28e
Merge pull request #2091 from boqwxp/printattrs 
Add `printattrs` command to print attributes of currently selected objects.
 2020-05-28 10:25:34 +00:00
Alberto Gonzalez 6228b10c9f
printattrs: Add test. 2020-05-27 08:00:00 +00:00
Eddie Hung 1dce798dc5 tests: add ecp5 latch testcase with -abc9 2020-05-25 16:39:16 -07:00
Eddie Hung a7f2ef6d34
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy 
xilinx: tidy up cells_sim.v a little
 2020-05-25 14:21:10 -07:00
Eddie Hung 08221edbc1 tests: xilinx macc test to have initval, shorten BMC depth for runtime 2020-05-25 10:09:05 -07:00
Eddie Hung 60aa804915 tests: fix some test warnings 2020-05-25 10:07:58 -07:00
Eddie Hung 9c6d216a06 tests: add test for abc9 -dff removing a redundant flop entirely 2020-05-25 08:43:33 -07:00
Eddie Hung 8dd93e389e tests: add testcase for abc9 -dff preserving flop names 2020-05-25 08:43:33 -07:00
Eddie Hung 95dcd7e785 test: add attribute-before-stmt test from @nakengelhardt 2020-05-25 07:36:53 -07:00
Eddie Hung 1c117ac023 verilog: do not warn for attributes on null statements 2020-05-25 07:36:53 -07:00
Eddie Hung 29d84339bf tests: add an generate-else test too 2020-05-25 07:36:53 -07:00
Eddie Hung 589775538c tests: add #2037 testcase 2020-05-25 07:36:53 -07:00
Eddie Hung 33b03ce904 xaiger: add testcase 2020-05-24 08:48:23 -07:00
Eddie Hung 574812d9a5
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr 
verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
 2020-05-21 11:00:36 -07:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Eddie Hung 2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff 
abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
 2020-05-18 08:06:50 -07:00
Eddie Hung e7fd8912f0 tests: attributes before task enable 2020-05-14 16:09:41 -07:00
Eddie Hung 73b7ea713c
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758 
opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too
 2020-05-14 11:56:22 -07:00
Eddie Hung 13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung 7cd3f4a79b abc9_ops: add -prep_bypass for auto bypass boxes; refactor 
Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier
 2020-05-14 10:33:56 -07:00
Eddie Hung 722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung 5ad3a85288 abc9: test to use box file instead of auto 2020-05-14 10:33:56 -07:00
Eddie Hung 48052ad813 abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
Eddie Hung 8d7b3c06b2 abc9: suppress warnings when no compatible + used flop boxes formed 2020-05-14 10:33:56 -07:00
Eddie Hung cdd250ef16 xilinx: update abc9_dff tests 2020-05-14 10:33:56 -07:00
Eddie Hung 762b6ad74a xilinx: remove no-longer-relevant test 2020-05-14 10:33:56 -07:00
Eddie Hung 5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042 
verilog: error if no direction given for task arguments, default to input in SV mode
 2020-05-14 09:45:54 -07:00
Claire Wolf 140e9a8e06
Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixes 
opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
 2020-05-14 18:31:16 +02:00
Claire Wolf ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto 
ast: swap range regardless of range_left >= 0
 2020-05-14 18:06:18 +02:00
Eddie Hung 56a5b1d2da test: add another testcase as per @nakengelhardt 2020-05-14 08:36:36 -07:00
Eddie Hung 5be4b00a0d opt_clean: improve warning message 2020-05-14 00:59:38 -07:00
Eddie Hung aa4a69f89b opt_clean: add init test 2020-05-14 00:31:08 -07:00
Eddie Hung 0d2c33f9f4 tests: update/extend task argument tests 2020-05-13 10:11:45 -07:00
Peter Crozier 17f050d3c6 Allow structs within structs. 2020-05-12 17:20:34 +01:00
Peter Crozier f482c9c016 Generalise structs and add support for packed unions. 2020-05-12 14:25:33 +01:00
Eddie Hung e5ce5a4fd5 tests: add #2042 testcase 2020-05-11 11:05:19 -07:00
Eddie Hung b11cf67a81 Setup tests/verilog properly 2020-05-11 10:31:02 -07:00
Eddie Hung 49e64ad492 test: update opt_expr_alu test 2020-05-08 11:12:58 -07:00
Eddie Hung 495acf9815 tests: opt_expr tests that depend on consumex 2020-05-08 11:07:11 -07:00
Peter Crozier 0b6b47ca67 Implement SV structs. 2020-05-08 14:40:49 +01:00
Dan Ravensloft 5b779f7f4e intel_alm: direct LUTRAM cell instantiation 
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.

While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
 2020-05-07 21:03:13 +02:00
Claire Wolf 0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990 
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
 2020-05-07 18:11:48 +02:00
Eddie Hung a299e606f8
Merge pull request #2028 from zachjs/master 
verilog: allow null gen-if then block
 2020-05-06 12:10:28 -07:00
Zachary Snow 8f9bba1bbf verilog: allow null gen-if then block 2020-05-06 08:43:02 -04:00
Eddie Hung 004999218f techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
Eddie Hung 7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src 
verilog: set src attribute for primitives
 2020-05-05 06:49:18 -07:00
whitequark 66d0ed2bcc ast/simplify: don't bitblast async ROMs declared as `logic`. 
Fixes #2020.
 2020-05-05 04:16:59 +00:00
Eddie Hung 2e911bc806 test: add failing test 2020-05-04 12:18:02 -07:00
Eddie Hung eb5eb60fd4 verilog: fix specify src attribute 2020-05-04 10:53:06 -07:00
Eddie Hung ad8e7878f6 tests: add tests for primitives' src 2020-05-04 10:21:47 -07:00
Claire Wolf 5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu 
Fix the other "opt_expr -fine" bug introduced in 213a89558
 2020-05-03 11:56:29 +02:00
Eddie Hung db13852ed6 test: add test for #2014 2020-05-02 14:22:37 -07:00
Eddie Hung 2e78daf1ca tests: aiger test for wire->start_offset != 0 2020-05-02 10:00:32 -07:00
Claire Wolf f38d76efbf Bugfix in partsel.v signed indices test cases 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-05-02 11:21:01 +02:00