Clifford Wolf
|
1cb25c05b3
|
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
|
2014-07-31 13:19:47 +02:00 |
Clifford Wolf
|
03c96f9ce7
|
Added "techmap -map %{design-name}"
|
2014-07-29 16:35:13 +02:00 |
Clifford Wolf
|
397b00252d
|
Added $shift and $shiftx cell types (needed for correct part select behavior)
|
2014-07-29 16:35:13 +02:00 |
Clifford Wolf
|
3c45277ee0
|
Added wire->upto flag for signals such as "wire [0:7] x;"
|
2014-07-28 12:12:13 +02:00 |
Clifford Wolf
|
7bd2d1064f
|
Using log_assert() instead of assert()
|
2014-07-28 11:27:48 +02:00 |
Clifford Wolf
|
d86a25f145
|
Added std::initializer_list<> constructor to SigSpec
|
2014-07-28 10:52:58 +02:00 |
Clifford Wolf
|
f99495a895
|
Added cover() to all SigSpec constructors
|
2014-07-28 10:52:30 +02:00 |
Clifford Wolf
|
c4bdba78cb
|
Added proper Design->addModule interface
|
2014-07-27 21:12:09 +02:00 |
Clifford Wolf
|
4be645860b
|
Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
|
2014-07-27 14:47:48 +02:00 |
Clifford Wolf
|
675cb93da9
|
Added RTLIL::Module::wire(id) and cell(id) lookup functions
|
2014-07-27 11:18:31 +02:00 |
Clifford Wolf
|
10e5791c5e
|
Refactoring: Renamed RTLIL::Design::modules to modules_
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
1c8fdaeef8
|
Added RTLIL::ObjIterator and RTLIL::ObjRange
|
2014-07-27 11:18:30 +02:00 |
Clifford Wolf
|
4c4b602156
|
Refactoring: Renamed RTLIL::Module::cells to cells_
|
2014-07-27 01:51:45 +02:00 |
Clifford Wolf
|
f9946232ad
|
Refactoring: Renamed RTLIL::Module::wires to wires_
|
2014-07-27 01:49:51 +02:00 |
Clifford Wolf
|
d68c993ed2
|
Changed more code to the new RTLIL::Wire constructors
|
2014-07-26 21:30:38 +02:00 |
Clifford Wolf
|
946ddff9ce
|
Changed a lot of code to the new RTLIL::Wire constructors
|
2014-07-26 20:12:50 +02:00 |
Clifford Wolf
|
97a59851a6
|
Added RTLIL::Cell::has(portname)
|
2014-07-26 16:11:28 +02:00 |
Clifford Wolf
|
f8fdc47d33
|
Manual fixes for new cell connections API
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
b7dda72302
|
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
|
2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
cd6574ecf6
|
Added some missing "const" in rtlil.h
|
2014-07-26 15:58:22 +02:00 |
Clifford Wolf
|
7ac9dc7f6e
|
Added RTLIL::Module::connections()
|
2014-07-26 15:58:21 +02:00 |
Clifford Wolf
|
b03aec6e32
|
Added RTLIL::Module::connect(const RTLIL::SigSig&)
|
2014-07-26 14:31:47 +02:00 |
Clifford Wolf
|
3719281ed4
|
Automatically pack SigSpec on copy/assign
|
2014-07-26 13:59:30 +02:00 |
Clifford Wolf
|
e75e495c2b
|
Added new RTLIL::Cell port access methods
|
2014-07-26 12:22:58 +02:00 |
Clifford Wolf
|
cc4f10883b
|
Renamed RTLIL::{Module,Cell}::connections to connections_
|
2014-07-26 11:58:03 +02:00 |
Clifford Wolf
|
4755e14e7b
|
Added copy-constructor-like module->addCell(name, other) method
|
2014-07-26 00:38:44 +02:00 |
Clifford Wolf
|
2bec47a404
|
Use only module->addCell() and module->remove() to create and delete cells
|
2014-07-25 17:56:19 +02:00 |
Clifford Wolf
|
c762050e7f
|
Added RTLIL::SigSpec is_chunk()/as_chunk() API
|
2014-07-25 14:23:10 +02:00 |
Clifford Wolf
|
7f1789ad1b
|
Fixed typo in cover id
|
2014-07-25 03:41:53 +02:00 |
Clifford Wolf
|
6aa792c864
|
Replaced more old SigChunk programming patterns
|
2014-07-24 23:10:58 +02:00 |
Clifford Wolf
|
e589289df7
|
Some improvements in SigSpec packing/unpacking and checking
|
2014-07-24 15:05:41 +02:00 |
Clifford Wolf
|
22ede43b3f
|
Small changes regarding cover() and check() in SigSpec
|
2014-07-24 04:46:36 +02:00 |
Clifford Wolf
|
798f713629
|
Added support for YOSYS_COVER_FILE env variable
|
2014-07-24 04:16:32 +02:00 |
Clifford Wolf
|
1b0d5fc22d
|
Added cover() calls to RTLIL::SigSpec methods
|
2014-07-24 03:50:28 +02:00 |
Clifford Wolf
|
82fa356037
|
Added hashing to RTLIL::SigSpec relational and equal operators
|
2014-07-23 23:58:03 +02:00 |
Clifford Wolf
|
f368d792fb
|
Disabled RTLIL::SigSpec::check() in release builds
|
2014-07-23 21:42:44 +02:00 |
Clifford Wolf
|
95ac484548
|
Fixed release build
|
2014-07-23 21:38:18 +02:00 |
Clifford Wolf
|
2a41afb7b2
|
Added RTLIL::SigSpec::repeat()
|
2014-07-23 21:34:14 +02:00 |
Clifford Wolf
|
c094c53de8
|
Removed RTLIL::SigSpec::optimize()
|
2014-07-23 20:32:28 +02:00 |
Clifford Wolf
|
8fd8e4a468
|
Turned RTLIL::SigSpec::optimize() to a no-op: a packed SigSpec is now always optimized
|
2014-07-23 20:11:55 +02:00 |
Clifford Wolf
|
a62c21c9c6
|
Removed RTLIL::SigSpec::expand() method
|
2014-07-23 19:34:51 +02:00 |
Clifford Wolf
|
85db102e13
|
Replaced RTLIL::SigSpec::operator!=() with inline version
|
2014-07-23 15:35:09 +02:00 |
Clifford Wolf
|
ec923652e2
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
|
2014-07-23 09:52:55 +02:00 |
Clifford Wolf
|
a8d3a68971
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
|
2014-07-23 09:49:43 +02:00 |
Clifford Wolf
|
260c19ec5a
|
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
|
2014-07-23 09:34:47 +02:00 |
Clifford Wolf
|
c61467a32c
|
Some cleanups in RTLIL::SigChunk::SigChunk(const RTLIL::Const&)
|
2014-07-23 08:59:54 +02:00 |
Clifford Wolf
|
115dd959d9
|
SigSpec refactoring: More cleanups of old SigSpec use pattern
|
2014-07-22 23:50:21 +02:00 |
Clifford Wolf
|
fd4cbe6275
|
SigSpec refactoring: rewrote some RTLIL::SigSpec methods to use unpacked form
|
2014-07-22 22:26:30 +02:00 |
Clifford Wolf
|
a97be0828a
|
Removed RTLIL::SigChunk::compare()
|
2014-07-22 21:40:52 +02:00 |
Clifford Wolf
|
08e1e25169
|
SigSpec refactoring: added RTLIL::SigSpec::bits() and pack/unpack api
|
2014-07-22 21:33:52 +02:00 |
Clifford Wolf
|
28b3fd05fa
|
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
|
2014-07-22 20:58:44 +02:00 |
Clifford Wolf
|
4b4048bc5f
|
SigSpec refactoring: using the accessor functions everywhere
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
16e5ae0b92
|
SigSpec refactoring: renamed the SigSpec members to chunks_ and width_ and added accessor functions
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
|
2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
1d88f1cf9f
|
Removed deprecated module->new_wire()
|
2014-07-21 12:35:06 +02:00 |
Clifford Wolf
|
54b0f2e659
|
Added module->remove(), module->addWire(), module->addCell(), cell->check()
|
2014-07-21 12:02:55 +02:00 |
Clifford Wolf
|
e57db5e9b2
|
Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
|
2014-07-20 11:01:04 +02:00 |
Clifford Wolf
|
2d69c309f9
|
Added function-like cell creation helpers
|
2014-07-18 10:27:06 +02:00 |
Clifford Wolf
|
274c514879
|
Fixed RTLIL::SigSpec::append_bit() for appending constants
|
2014-07-17 12:10:57 +02:00 |
Clifford Wolf
|
73e0e13d2f
|
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
|
2014-07-16 11:38:02 +02:00 |
Clifford Wolf
|
e275e8eef9
|
Add support for cell arrays
|
2014-06-07 11:48:50 +02:00 |
Clifford Wolf
|
d4a1b0af5b
|
Added support for dlatchsr cells
|
2014-03-31 14:14:40 +02:00 |
Clifford Wolf
|
e164edc8d1
|
Fixed typo in RTLIL::Module::addAdff()
|
2014-03-17 14:41:41 +01:00 |
Clifford Wolf
|
ef1795a1e8
|
Fixed typo in RTLIL::Module::{addSshl,addSshr}
|
2014-03-15 22:52:10 +01:00 |
Clifford Wolf
|
b7c71d92f6
|
Added RTLIL::Module::add{Dff,Dffsr,Adff,Dlatch}Gate() API
|
2014-03-15 14:35:29 +01:00 |
Clifford Wolf
|
0ac915a757
|
Progress in Verific bindings
|
2014-03-14 11:46:13 +01:00 |
Clifford Wolf
|
77e5968323
|
Added RTLIL::Module::Add{Inv,And,Or,Xor,Mux}Gate API
|
2014-03-14 11:45:44 +01:00 |
Clifford Wolf
|
fad8558eb5
|
Merged OSX fixes from Siesh1oo with some modifications
|
2014-03-13 12:48:10 +01:00 |
Clifford Wolf
|
78c64a6401
|
Fixed a typo in RTLIL::Module::addReduce...
|
2014-03-10 12:07:26 +01:00 |
Clifford Wolf
|
fdef064b1d
|
Added RTLIL::Module::add... helper methods
|
2014-03-10 03:02:27 +01:00 |
Clifford Wolf
|
8f9c707a4c
|
Improved checking of internal cell conventions
|
2014-02-08 19:13:49 +01:00 |
Clifford Wolf
|
fc3b3c4ec3
|
Added $slice and $concat cell types
|
2014-02-07 17:44:57 +01:00 |
Clifford Wolf
|
a1ac710ab8
|
Stronger checking of internal cells
|
2014-02-07 17:39:35 +01:00 |
Clifford Wolf
|
fa295a4528
|
Added generic RTLIL::SigSpec::parse_sel() with support for selection variables
|
2014-02-06 19:22:46 +01:00 |
Clifford Wolf
|
a6750b3753
|
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
|
2014-02-03 13:01:45 +01:00 |
Clifford Wolf
|
f9c4d33909
|
Added RTLIL::SigSpec::to_single_sigbit()
|
2014-02-02 21:35:26 +01:00 |
Clifford Wolf
|
1e67099b77
|
Added $assert cell
|
2014-01-19 14:03:40 +01:00 |
Clifford Wolf
|
eec2cd1e78
|
Added RTLIL::SigSpec::optimized() API
|
2014-01-03 02:43:31 +01:00 |
Clifford Wolf
|
fb2bf934dc
|
Added correct handling of $memwr priority
|
2014-01-03 00:22:17 +01:00 |
Clifford Wolf
|
15acf593e7
|
Added additional checks for A_SIGNED == B_SIGNED for cells with that constraint
|
2013-12-31 14:54:06 +01:00 |
Clifford Wolf
|
c69c416d28
|
Added $bu0 cell (for easy correct $eq/$ne mapping)
|
2013-12-28 12:02:14 +01:00 |
Clifford Wolf
|
369bf81a70
|
Added support for non-const === and !== (for miter circuits)
|
2013-12-27 14:20:15 +01:00 |
Clifford Wolf
|
5d83904746
|
Fixes and improvements in RTLIL::SigSpec::parse
|
2013-12-07 11:57:29 +01:00 |
Clifford Wolf
|
f4b46ed31e
|
Replaced signed_parameters API with CONST_FLAG_SIGNED
|
2013-12-04 14:24:44 +01:00 |
Clifford Wolf
|
93a70959f3
|
Replaced RTLIL::Const::str with generic decoder method
|
2013-12-04 14:14:05 +01:00 |
Clifford Wolf
|
f71e27dbf1
|
Remove auto_wire framework (smarter than the verilog standard)
|
2013-11-24 17:29:11 +01:00 |
Clifford Wolf
|
609caa23b5
|
Implemented correct handling of signed module parameters
|
2013-11-24 17:17:21 +01:00 |
Clifford Wolf
|
18d003254c
|
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
|
2013-11-22 04:41:20 +01:00 |
Clifford Wolf
|
8e58bb330d
|
Added SigBit struct and refactored RTLIL::SigSpec::extract
|
2013-11-22 04:07:13 +01:00 |
Clifford Wolf
|
0fd3ebdb23
|
Added information on all internal cell types to internal checker
|
2013-11-11 00:13:18 +01:00 |
Clifford Wolf
|
223892ac28
|
Improved user-friendliness of "sat" and "eval" expression parsing
|
2013-11-09 12:02:27 +01:00 |
Clifford Wolf
|
947bd9b96b
|
Renamed extend_un0() to extend_u0() and use it in genrtlil
|
2013-11-07 18:17:10 +01:00 |
Clifford Wolf
|
0e1661f84e
|
Fixed type of sign extension in opt_const $eq/$ne handling
|
2013-11-07 16:53:28 +01:00 |
Clifford Wolf
|
f94266bb42
|
Added eval -vloghammer_report mode
|
2013-11-06 04:14:56 +01:00 |
Clifford Wolf
|
8e8f1994b8
|
Changed NEW_WIRE API to return the wire, not the signal
|
2013-10-18 14:19:45 +02:00 |
Clifford Wolf
|
cc5e379eca
|
Added RTLIL NEW_WIRE macro
|
2013-10-18 13:25:24 +02:00 |
Clifford Wolf
|
0f38008ed3
|
Added "design" command (-reset, -save, -load)
|
2013-07-27 14:27:51 +02:00 |
Clifford Wolf
|
21e38bed98
|
Added "eval" pass
|
2013-06-19 09:30:37 +02:00 |
Clifford Wolf
|
6971c4db62
|
Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API
|
2013-06-18 17:11:13 +02:00 |
Clifford Wolf
|
21d9251e52
|
Added "dump" command (part ilang backend)
|
2013-06-02 17:53:30 +02:00 |
Clifford Wolf
|
88af5b6a16
|
Improved opt_share for reduce cells
|
2013-03-29 11:19:21 +01:00 |
Clifford Wolf
|
041c06bd9d
|
Create nice errors when calling RTLIL::Module::derive() of base class
|
2013-03-26 19:27:49 +01:00 |
Clifford Wolf
|
7764d0ba1d
|
initial import
|
2013-01-05 11:13:26 +01:00 |