Eddie Hung
|
2fa3857963
|
Merge remote-tracking branch 'origin/master' into xaig_arrival
|
2019-09-02 12:13:44 -07:00 |
Eddie Hung
|
4aa505d1b2
|
Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc
ice40_dsp to allow signed multipliers
|
2019-09-01 10:11:33 -07:00 |
Miodrag Milanovic
|
fa5065e9b5
|
Fix select command error msg, fixes issue #1081
|
2019-09-01 11:00:09 +02:00 |
Eddie Hung
|
a09e69dd56
|
Fine tune xilinx_dsp pattern matcher
|
2019-08-30 16:18:58 -07:00 |
Eddie Hung
|
8f503fe3e6
|
autoremove ffM
|
2019-08-30 15:30:04 -07:00 |
Eddie Hung
|
e67f049e3b
|
Remove debug
|
2019-08-30 15:03:43 -07:00 |
Eddie Hung
|
15bab02a1b
|
ffM before addAB
|
2019-08-30 15:03:12 -07:00 |
Eddie Hung
|
c497114e94
|
Another oops
|
2019-08-30 15:02:53 -07:00 |
Eddie Hung
|
44a35015b3
|
Update commented out
|
2019-08-30 15:01:38 -07:00 |
Eddie Hung
|
390cf34d0a
|
Add support for ffM
|
2019-08-30 15:00:56 -07:00 |
Eddie Hung
|
2983a35dc0
|
Update comment
|
2019-08-30 15:00:40 -07:00 |
Eddie Hung
|
17b77fd411
|
Missing dep for test_pmgen
|
2019-08-30 14:01:07 -07:00 |
Eddie Hung
|
89359b6927
|
Missing dep for test_pmgen
|
2019-08-30 14:00:40 -07:00 |
Eddie Hung
|
723815b384
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-08-30 13:26:19 -07:00 |
Eddie Hung
|
c7f1ccbcb0
|
Merge remote-tracking branch 'origin/master' into xaig_arrival
|
2019-08-30 12:28:35 -07:00 |
Eddie Hung
|
999fb33fd0
|
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
abc9 to not call "clean" at end of run (often called outside)
|
2019-08-30 12:27:09 -07:00 |
Eddie Hung
|
c1459bc748
|
Do not restrict multiplier to unsigned
|
2019-08-30 12:22:14 -07:00 |
Eddie Hung
|
4e782f1509
|
New pmgen requires explicit accept
|
2019-08-30 11:02:10 -07:00 |
Eddie Hung
|
d2d2816f8c
|
Merge branch 'eddie/xilinx_srl' into xaig_arrival
|
2019-08-30 10:30:54 -07:00 |
Eddie Hung
|
f0fef90e9d
|
Merge remote-tracking branch 'origin/master' into xaig_arrival
|
2019-08-30 10:30:46 -07:00 |
Eddie Hung
|
295c18bd6b
|
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
|
2019-08-30 09:50:20 -07:00 |
Eddie Hung
|
6e475484b2
|
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
|
2019-08-30 09:37:32 -07:00 |
David Shah
|
6919c0f9b0
|
Merge branch 'master' into xc7dsp
|
2019-08-30 13:57:15 +01:00 |
Eddie Hung
|
18cabe9370
|
Output has priority over input when stitching in abc9
|
2019-08-29 17:24:03 -07:00 |
Eddie Hung
|
3e0f73c3df
|
abc9 to not call "clean" at end of run (often called outside)
|
2019-08-29 12:12:59 -07:00 |
Eddie Hung
|
1467761060
|
Fix typo that's gone unnoticed for 5 months!?!
|
2019-08-29 10:33:28 -07:00 |
Eddie Hung
|
c4e5310823
|
Use a dummy box file if none specified
|
2019-08-28 20:58:55 -07:00 |
Eddie Hung
|
116c249601
|
-auto-top should check $abstract (deferred) modules with (* top *)
|
2019-08-28 19:59:25 -07:00 |
Eddie Hung
|
4eb5847dbd
|
Cleanup
|
2019-08-28 18:10:33 -07:00 |
Eddie Hung
|
0af64df10c
|
Account for D port being a constant
|
2019-08-28 15:32:38 -07:00 |
Eddie Hung
|
a45c09c8d1
|
Account for D port being a constant
|
2019-08-28 15:31:55 -07:00 |
Eddie Hung
|
1b08f861b6
|
Merge branch 'eddie/xilinx_srl' into xaig_arrival
|
2019-08-28 15:31:48 -07:00 |
Eddie Hung
|
8d820a9884
|
Merge remote-tracking branch 'origin/master' into xaig_arrival
|
2019-08-28 15:19:10 -07:00 |
Eddie Hung
|
fc727fa5c9
|
Merge pull request #1334 from YosysHQ/clifford/async2synclatch
Add $dlatch support to async2sync
|
2019-08-28 12:36:06 -07:00 |
Eddie Hung
|
52c4655de3
|
No need to replace Q of slice since $shiftx is autoremove-d
|
2019-08-28 11:06:11 -07:00 |
Eddie Hung
|
11e3eb1009
|
More cleanup
|
2019-08-28 10:19:35 -07:00 |
Eddie Hung
|
86b538bd02
|
More cleanup
|
2019-08-28 10:11:09 -07:00 |
Eddie Hung
|
c4d1bd988b
|
Do not use default_params dict, hardcode default values, cleanup
|
2019-08-28 10:06:40 -07:00 |
Eddie Hung
|
c3e9627afe
|
Always generate if no match
|
2019-08-28 09:54:56 -07:00 |
Eddie Hung
|
0ebe2c9831
|
Rename test_pmgen arg xilinx_srl.{fixed,variable}
|
2019-08-28 09:27:03 -07:00 |
Eddie Hung
|
ba5d81c7f1
|
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
|
2019-08-28 09:21:03 -07:00 |
Clifford Wolf
|
47ffbf554e
|
Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-28 10:06:42 +02:00 |
Clifford Wolf
|
0fda0e821c
|
Add "paramap" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-28 10:03:27 +02:00 |
Clifford Wolf
|
c499dc3e73
|
Add $dlatch support to async2sync
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-28 09:45:22 +02:00 |
Clifford Wolf
|
70c0cddb1e
|
Merge pull request #1325 from YosysHQ/eddie/sat_init
In sat: 'x' in init attr should be ignored
|
2019-08-28 00:18:14 +02:00 |
Eddie Hung
|
28133432be
|
Ignore all 1'bx in (* init *)
|
2019-08-27 09:24:59 -07:00 |
Marcin Kościelnicki
|
5fb4b12cb5
|
improve clkbuf_inhibit propagation upwards through hierarchy
|
2019-08-27 17:26:47 +02:00 |
Eddie Hung
|
9172d4a674
|
Missing close bracket
|
2019-08-26 21:02:52 -07:00 |
Eddie Hung
|
6b5e65919a
|
Revert "In sat: 'x' in init attr should not override constant"
This reverts commit 2b37a093e9 .
|
2019-08-26 17:52:57 -07:00 |
Eddie Hung
|
54422c5bb4
|
Remove leftover header
|
2019-08-26 17:51:13 -07:00 |
Eddie Hung
|
e95fb24574
|
Improve xilinx_srl.fixed generate, add .variable generate
|
2019-08-26 17:49:08 -07:00 |
Eddie Hung
|
45c34c87ee
|
Account for maxsubcnt overflowing
|
2019-08-26 17:48:54 -07:00 |
Eddie Hung
|
b32d6bf403
|
Add xilinx_srl_pm.variable to test_pmgen
|
2019-08-26 17:44:57 -07:00 |
Eddie Hung
|
e574edc3e9
|
Populate generate for xilinx_srl.fixed pattern
|
2019-08-26 14:21:17 -07:00 |
Eddie Hung
|
cf9e017127
|
Add xilinx_srl_fixed, fix typos
|
2019-08-26 14:20:06 -07:00 |
Eddie Hung
|
a098205479
|
Merge branch 'master' into mwk/xilinx_bufgmap
|
2019-08-26 13:25:17 -07:00 |
Eddie Hung
|
7911143827
|
Create new $__XILINX_SHREG_ cell for variable length too
|
2019-08-23 18:15:49 -07:00 |
Eddie Hung
|
a048fc93e8
|
Do not allow Q of last cell of variable length SRL to be (* keep *)
|
2019-08-23 18:15:24 -07:00 |
Eddie Hung
|
ee9f6e6243
|
Also add first.Q to chain_bits since variable length
|
2019-08-23 18:14:06 -07:00 |
Eddie Hung
|
70ce3d0670
|
Do not enforce !EN_POLARITY on $dffe
|
2019-08-23 18:11:28 -07:00 |
Eddie Hung
|
188b49378a
|
Create new cell for fixed length SRL
|
2019-08-23 17:25:30 -07:00 |
Eddie Hung
|
e081303ee8
|
Cleanup FDRE matching
|
2019-08-23 17:23:52 -07:00 |
Eddie Hung
|
54488cfb82
|
Oops don't need a finally block
|
2019-08-23 16:39:37 -07:00 |
Eddie Hung
|
83e2d87fb8
|
Keep track of bits in variable length chain, to check for taps
|
2019-08-23 16:21:10 -07:00 |
Eddie Hung
|
f2d4814284
|
Don't forget $dff has no EN
|
2019-08-23 16:14:57 -07:00 |
Eddie Hung
|
2217d926a9
|
Same for variable length
|
2019-08-23 16:13:16 -07:00 |
Eddie Hung
|
b1caf7be5e
|
Filter on en_port for fixed length
|
2019-08-23 16:09:46 -07:00 |
Eddie Hung
|
513af10d77
|
Check clock is consistent
|
2019-08-23 15:18:26 -07:00 |
Eddie Hung
|
c762618783
|
Fix last_cell.D
|
2019-08-23 15:08:49 -07:00 |
Eddie Hung
|
ca5de78e76
|
Revert "Add a unique argument to pmgen's nusers()"
This reverts commit 1d88887cfd .
|
2019-08-23 15:04:00 -07:00 |
Eddie Hung
|
e85e6e8d45
|
Revert "Fix polarity"
This reverts commit 9cd23cf0fe .
|
2019-08-23 15:03:42 -07:00 |
Eddie Hung
|
9cd23cf0fe
|
Fix polarity
|
2019-08-23 14:49:34 -07:00 |
Eddie Hung
|
c2757613b6
|
Check for non unique nusers/fanouts
|
2019-08-23 14:32:36 -07:00 |
Eddie Hung
|
1d88887cfd
|
Add a unique argument to pmgen's nusers()
|
2019-08-23 14:32:17 -07:00 |
Eddie Hung
|
8ecfd55d5a
|
Update doc
|
2019-08-23 14:16:41 -07:00 |
Eddie Hung
|
3d7f4aa0c8
|
Remove (* init *) entry when consumed into SRL
|
2019-08-23 13:56:01 -07:00 |
Eddie Hung
|
48c424e45b
|
Cleanup
|
2019-08-23 13:46:05 -07:00 |
Eddie Hung
|
967a36c125
|
indo -> into
|
2019-08-23 13:16:50 -07:00 |
Eddie Hung
|
a1f78eab04
|
indo -> into
|
2019-08-23 13:15:41 -07:00 |
Eddie Hung
|
5939ffdc07
|
Forgot to slice
|
2019-08-23 13:06:59 -07:00 |
Eddie Hung
|
242b3083ea
|
Cope with possibility that D could connect to Q on same cell
|
2019-08-23 13:06:31 -07:00 |
Eddie Hung
|
18b64609c2
|
xilinx_srl to use 'slice' features of pmgen for word level
|
2019-08-23 12:22:06 -07:00 |
Eddie Hung
|
f4fd41d5d2
|
Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
|
2019-08-23 11:35:06 -07:00 |
Eddie Hung
|
78b7d8f531
|
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
|
2019-08-23 11:32:44 -07:00 |
Eddie Hung
|
d672b1ddec
|
Merge remote-tracking branch 'origin/master' into xaig_arrival
|
2019-08-23 11:26:55 -07:00 |
Eddie Hung
|
619f2414e5
|
clkbufmap to only check clkbuf_inhibit if no selection given
|
2019-08-23 11:14:42 -07:00 |
Eddie Hung
|
4d89c3f468
|
Review comment from @cliffordwolf
|
2019-08-23 10:03:41 -07:00 |
Eddie Hung
|
6872805a3e
|
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
|
2019-08-23 10:00:50 -07:00 |
Clifford Wolf
|
55bf8f69e0
|
Fix port hanlding in pmgen
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-23 16:26:54 +02:00 |
Clifford Wolf
|
adb81ba386
|
Add pmgen slices and choices
Signed-off-by: Clifford Wolf <clifford@clifford.at>
|
2019-08-23 16:15:50 +02:00 |
Eddie Hung
|
51ffb093b5
|
In sat: 'x' in init attr should not override constant
|
2019-08-22 16:43:08 -07:00 |
Eddie Hung
|
2b37a093e9
|
In sat: 'x' in init attr should not override constant
|
2019-08-22 16:42:19 -07:00 |
Eddie Hung
|
53fed4f7e9
|
Actually, there might not be any harm in updating sigmap...
|
2019-08-22 16:16:56 -07:00 |
Eddie Hung
|
cfafd360d5
|
Add comment as per @cliffordwolf
|
2019-08-22 16:16:56 -07:00 |
Eddie Hung
|
8691596d19
|
Revert "Try way that doesn't involve creating a new wire"
This reverts commit 2f427acc9e .
|
2019-08-22 16:16:34 -07:00 |
Eddie Hung
|
5ff75b1cdc
|
Try way that doesn't involve creating a new wire
|
2019-08-22 16:16:34 -07:00 |
Eddie Hung
|
e1fff34dde
|
If d_bit already in sigbit_chain_next, create extra wire
|
2019-08-22 16:16:34 -07:00 |
Eddie Hung
|
c50d68653d
|
Spelling
|
2019-08-22 16:06:36 -07:00 |
Eddie Hung
|
6e8fda8bf0
|
Add doc
|
2019-08-22 11:52:24 -07:00 |
Eddie Hung
|
cabadb85e2
|
Add copyright
|
2019-08-22 11:25:19 -07:00 |
Eddie Hung
|
36d94caec1
|
Remove `shregmap -tech xilinx` additions
|
2019-08-22 11:22:09 -07:00 |
Eddie Hung
|
9f3ed1726e
|
pmgen to also iterate over all module ports
|
2019-08-22 11:15:16 -07:00 |
Eddie Hung
|
74bd190d3b
|
Remove output_bits
|
2019-08-22 11:14:59 -07:00 |
Eddie Hung
|
231ddbf95c
|
Forgot to set ud_variable.minlen
|
2019-08-22 11:02:17 -07:00 |
Eddie Hung
|
61639d5387
|
Do not run xilinx_srl_pm in fixed loop
|
2019-08-22 10:51:04 -07:00 |
Eddie Hung
|
7188972645
|
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
|
2019-08-22 10:32:54 -07:00 |
Eddie Hung
|
d0b2973413
|
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
|
2019-08-22 10:32:06 -07:00 |
Eddie Hung
|
b800059fc1
|
Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
opt_expr to trim A port of $shiftx/$shift
|
2019-08-22 10:31:27 -07:00 |
Eddie Hung
|
9245f0d3f5
|
Copy-paste typo
|
2019-08-22 08:43:44 -07:00 |
Eddie Hung
|
6f971470f8
|
Respect opt_expr -keepdc as per @cliffordwolf
|
2019-08-22 08:37:27 -07:00 |
Eddie Hung
|
379f33af54
|
Handle $shift and Y_WIDTH > 1 as per @cliffordwolf
|
2019-08-22 08:22:23 -07:00 |
Eddie Hung
|
9e31f01b34
|
Add cover()
|
2019-08-22 08:06:24 -07:00 |
Eddie Hung
|
d0ffe7544c
|
Canonical form
|
2019-08-22 08:05:01 -07:00 |
Eddie Hung
|
d3a212ff91
|
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
|
2019-08-21 21:53:55 -07:00 |
Eddie Hung
|
7d02d17b16
|
Reuse var
|
2019-08-21 19:18:40 -07:00 |
Eddie Hung
|
5c8344363f
|
Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit 7e7965ca7b .
|
2019-08-21 19:18:27 -07:00 |
Eddie Hung
|
c7859531c2
|
opt_expr to trim A port of $shiftx if Y_WIDTH == 1
|
2019-08-21 19:18:05 -07:00 |
Eddie Hung
|
7e7965ca7b
|
Trim shiftx_width when upper bits are 1'bx
|
2019-08-21 18:43:17 -07:00 |
Eddie Hung
|
ed7be3e6b6
|
Add comment
|
2019-08-21 17:36:38 -07:00 |
Eddie Hung
|
15188033da
|
Add variable length support to xilinx_srl
|
2019-08-21 17:34:40 -07:00 |
Eddie Hung
|
6d76ae4c65
|
Rename pattern to fixed
|
2019-08-21 15:46:58 -07:00 |
Eddie Hung
|
b0a3b430bf
|
attribute -> attr
|
2019-08-21 15:44:07 -07:00 |
Eddie Hung
|
61b4d7ae13
|
Use Cell::has_keep_attribute()
|
2019-08-21 15:41:46 -07:00 |
Eddie Hung
|
6fa9e03e4c
|
xilinx_srl to support FDRE and FDRE_1
|
2019-08-21 15:35:29 -07:00 |
Eddie Hung
|
3c8e8521a6
|
Fix polarity of EN_POL
|
2019-08-21 14:42:11 -07:00 |
Eddie Hung
|
a980f0d4be
|
Add CLKPOL == 0
|
2019-08-21 14:35:40 -07:00 |
Eddie Hung
|
1c7d721558
|
Reject if not minlen from inside pattern matcher
|
2019-08-21 14:26:24 -07:00 |
Eddie Hung
|
cab2bd083e
|
Get wire via SigBit
|
2019-08-21 13:47:47 -07:00 |
Eddie Hung
|
52fea5b658
|
Respect \keep on cells or wires
|
2019-08-21 13:42:03 -07:00 |
Eddie Hung
|
5ce0c31d0e
|
Add init support
|
2019-08-21 13:05:10 -07:00 |
Eddie Hung
|
df53fe12e7
|
Fix spacing
|
2019-08-21 12:54:11 -07:00 |
Eddie Hung
|
0250712486
|
Initial progress on xilinx_srl
|
2019-08-21 12:50:49 -07:00 |
Eddie Hung
|
8f69be9cc7
|
Merge remote-tracking branch 'origin/master' into xaig_arrival
|
2019-08-21 11:39:14 -07:00 |
Miodrag Milanovic
|
948b6f91a1
|
Fix test_pmgen deps
|
2019-08-21 17:00:24 +02:00 |
Clifford Wolf
|
7d8db1c053
|
Merge pull request #1314 from YosysHQ/eddie/fix_techmap
techmap -max_iter to apply to each module individually
|
2019-08-21 09:12:56 +02:00 |
Eddie Hung
|
4cc74346f1
|
Fix compile error
|
2019-08-20 20:27:05 -07:00 |
Eddie Hung
|
9b9d759451
|
Fix copy-paste typo
|
2019-08-20 20:18:51 -07:00 |
Eddie Hung
|
b7a48e3e0f
|
Merge remote-tracking branch 'origin/master' into xc7dsp
|
2019-08-20 20:18:17 -07:00 |
Eddie Hung
|
affe9c9c1a
|
Merge branch 'eddie/fix_techmap' into xaig_arrival
|
2019-08-20 20:06:47 -07:00 |
Eddie Hung
|
fe61dcce8b
|
Grammar
|
2019-08-20 20:05:51 -07:00 |
Eddie Hung
|
193eae0c84
|
techmap -max_iter to apply to each module individually
|
2019-08-20 19:50:20 -07:00 |
Eddie Hung
|
57493e328a
|
techmap -max_iter to apply to each module individually
|
2019-08-20 19:48:16 -07:00 |
Eddie Hung
|
091bf4a18b
|
Remove sequential extension
|
2019-08-20 18:16:37 -07:00 |
Eddie Hung
|
fad15d276d
|
retime_mode -> dff_mode
|
2019-08-20 18:08:58 -07:00 |
Eddie Hung
|
505d062daf
|
Fix use of {CLK,EN}_POLARITY, also add a FIXME
|
2019-08-20 13:33:31 -07:00 |
Eddie Hung
|
c4d4c6db3f
|
Merge remote-tracking branch 'origin/master' into xaig_dff
|
2019-08-20 12:00:12 -07:00 |
Eddie Hung
|
14c03861b6
|
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
Refactor abc9 to use port attributes, not module attributes
|
2019-08-20 11:59:31 -07:00 |
Clifford Wolf
|
d0117d7d12
|
Merge branch 'master' into clifford/pmgen
|
2019-08-20 11:39:23 +02:00 |
whitequark
|
749ff864aa
|
Merge pull request #1309 from whitequark/proc_clean-fix-1268
proc_clean: fix order of switch insertion
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2019-08-20 00:45:41 +00:00 |
Eddie Hung
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1f03154a0c
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-19 15:19:32 -07:00 |