tangxifan
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64294ae4eb
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[Doc] Update README for architecture files due to new architecture features
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2021-04-16 19:25:54 -06:00 |
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tangxifan
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ff4460695b
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[HDL] Add dff tech map files for yosys
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2021-04-16 17:00:55 -06:00 |
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tangxifan
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e46c6e75a3
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[Benchmark] Add missing RTL for IWLS2005 benchmarks
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2021-04-16 16:50:41 -06:00 |
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tangxifan
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87587bbb74
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[Test] Add iwls2005 benchmarks to regression tests
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2021-04-16 16:12:05 -06:00 |
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tangxifan
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1566a5558a
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[Test] Add task configuration file for iwls2005
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2021-04-16 16:10:31 -06:00 |
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tangxifan
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43bf016576
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[Script] Add example openfpga shell script for iwls benchmark
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2021-04-16 16:09:47 -06:00 |
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tangxifan
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26d3b5a954
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[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches
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2021-04-16 16:08:58 -06:00 |
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tangxifan
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86ad572530
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[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks
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2021-04-16 14:27:54 -06:00 |
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tangxifan
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b469705819
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Merge branch 'master' into fpga_sdc_test
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2021-04-11 21:14:46 -06:00 |
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tangxifan
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1db8bd7eec
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[Test] Update regression test with new SDC tests
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2021-04-11 20:24:32 -06:00 |
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tangxifan
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07f6066c11
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[Script] Update timing unit in SDC example script
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2021-04-11 20:24:18 -06:00 |
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tangxifan
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94c4c817eb
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[Test] Expand sdc time unit test to sweep all the available units
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2021-04-11 20:14:09 -06:00 |
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tangxifan
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a4893e27cf
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[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
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2021-04-11 17:26:27 -06:00 |
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tangxifan
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44d97ead86
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Merge branch 'master' into hetergeneous_arch
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2021-03-23 17:05:03 -06:00 |
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tangxifan
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b00b4f0f5f
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[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
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2021-03-23 15:44:53 -06:00 |
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tangxifan
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d82ffe0cbf
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[Test] Deploy MAC_8 benchmark to regression test
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2021-03-23 15:36:28 -06:00 |
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tangxifan
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108c84a022
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[HDL] Add HDL for 8-bit single-mode multiplier
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2021-03-23 15:36:09 -06:00 |
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tangxifan
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145a80de43
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[Script] Add an openfpga shell script for heterogeneous fpga verification
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2021-03-23 15:35:34 -06:00 |
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tangxifan
|
fdec72b5bc
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[Arch] Add an example architecture with 8-bit single-mode multiplier
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2021-03-23 15:35:06 -06:00 |
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tangxifan
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be03eafd66
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[Benchmark] Add a micro benchmark: 8-bit multiply and accumulate
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2021-03-23 15:33:37 -06:00 |
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tangxifan
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8c970a792a
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[Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier
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2021-03-23 15:33:00 -06:00 |
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tangxifan
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6b0409da60
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[Script] Add a template yosys script support only DSP mapping
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2021-03-23 15:32:10 -06:00 |
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tangxifan
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a4bbffd1aa
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[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
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2021-03-23 15:30:41 -06:00 |
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tangxifan
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fff16a01ab
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[Test] Update tolerance when checking VTR benchmark QoR
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2021-03-23 12:27:20 -06:00 |
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tangxifan
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781880ed93
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[Script] Add tolerance options to check qor script
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2021-03-23 12:26:33 -06:00 |
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tangxifan
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e3f8a6cf7a
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[Test] Deploy QoR check to VTR benchmark regression test
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2021-03-23 11:15:22 -06:00 |
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tangxifan
|
351dec5935
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[Test] Add QoR csv file for vtr benchmarks
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2021-03-23 11:15:02 -06:00 |
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tangxifan
|
23e7f7f1f5
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[Script] Update default list of result extraction for openfpga flow
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2021-03-23 11:06:42 -06:00 |
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tangxifan
|
adfbd28a7a
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[Script] Add a simple QoR checker
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2021-03-23 11:06:16 -06:00 |
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tangxifan
|
61eddb08de
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[Test] Update task configuration by commenting out high-runtime VTR benchmarks
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2021-03-22 14:42:42 -06:00 |
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tangxifan
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55d1004cf2
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[Benchmark] Add missing DPRAM module to LU32PEEng
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2021-03-22 14:41:38 -06:00 |
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tangxifan
|
5fc83ebea3
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[Benchmark] Add missing DPRAM modules to LU8PEEng
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2021-03-22 14:38:00 -06:00 |
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tangxifan
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b828f91a78
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[Benchmark] Add missing DPRAM and SPRAM modules to mcml
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2021-03-22 14:13:05 -06:00 |
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tangxifan
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d050f1b746
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[Script] Enable fast bitstream generation for VTR benchmarks
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2021-03-22 12:54:36 -06:00 |
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tangxifan
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4bfd0c0a02
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[Test] Enable more VTR benchmark in testing
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2021-03-22 12:53:30 -06:00 |
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tangxifan
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b906ab814e
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[Benchmark] Add missing DPRAM module to mkPktMerge
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2021-03-22 12:51:23 -06:00 |
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tangxifan
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310c2a9495
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[Benchmark] Add missing DPRAM module to mkDelayWorker32B
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2021-03-22 12:51:02 -06:00 |
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tangxifan
|
707247283c
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[Benchmark] Add missing DPRAM module to mkSMAdapter4B
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2021-03-22 12:50:39 -06:00 |
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tangxifan
|
eb056e2afd
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[Benchmark] Add missing DPRAM module to or1200
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2021-03-22 12:50:17 -06:00 |
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tangxifan
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7fd345a616
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[Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs
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2021-03-22 10:39:47 -06:00 |
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tangxifan
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cc10b10703
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[Test] Enable more benchmarks for testing; See problems when mapping BRAMs
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2021-03-20 22:53:37 -06:00 |
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tangxifan
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169ee53b79
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[Benchmark] Add missing modules to VTR benchmarks
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2021-03-20 22:53:17 -06:00 |
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tangxifan
|
eca2a35612
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[Script] Add route chan width option to vtr openfpga script
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2021-03-20 22:00:09 -06:00 |
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tangxifan
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9a3aff274f
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[Test] Use fix routing channel width to save runtime for VTR benchmarks
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2021-03-20 21:59:44 -06:00 |
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tangxifan
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ca9a70fc88
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[Test] Comment out benchmarks have problems in synthesis
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2021-03-20 21:29:21 -06:00 |
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tangxifan
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125e94a6b3
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[Test] Add full VTR benchmark (with most commented); ready for massive testing
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2021-03-20 21:01:18 -06:00 |
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tangxifan
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2bd8ef2af9
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[Benchmark] Patch boundtop.v with missing SPRAM module
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2021-03-20 21:00:53 -06:00 |
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tangxifan
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cb07848475
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[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
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2021-03-20 18:11:54 -06:00 |
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tangxifan
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f3792bc6f6
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[Test] Update VTR benchmark test case to include DSP example benchmark
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2021-03-20 18:09:19 -06:00 |
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tangxifan
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477a522885
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[HDL] Rename tech lib to be consistent with arch name changes
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2021-03-20 18:08:03 -06:00 |
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tangxifan
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911979a731
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[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
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2021-03-20 18:04:59 -06:00 |
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tangxifan
|
1185f7b8bf
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[Script] Add a template yosys script to enable DSP mapping
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2021-03-20 17:05:30 -06:00 |
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tangxifan
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6bf4880c50
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[benchmark] Add vtr benchmark
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2021-03-17 15:24:26 -06:00 |
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tangxifan
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f9dc7c1b54
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[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
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2021-03-17 15:15:22 -06:00 |
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tangxifan
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08a86e056a
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[Test] Add vtr benchmark regression test
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2021-03-17 15:13:58 -06:00 |
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tangxifan
|
7eeb35d21f
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[Script] Bug fix in yosys script to synthesis BRAM
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2021-03-17 15:12:04 -06:00 |
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tangxifan
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1976a8068f
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[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
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2021-03-17 15:11:17 -06:00 |
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tangxifan
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deee7ba366
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[Script] Add example script to run vtr benchmarks
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2021-03-17 15:10:56 -06:00 |
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tangxifan
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910f8471dd
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[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
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2021-03-17 15:10:05 -06:00 |
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tangxifan
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76113a80fa
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[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
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2021-03-17 15:09:12 -06:00 |
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tangxifan
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e1f8b252b1
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Merge branch 'master' into yosys_heterogeneous_block_support
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2021-03-16 20:05:21 -06:00 |
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tangxifan
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d12a8a03fd
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[Test] Update test case using yosys bram parameters
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2021-03-16 19:52:17 -06:00 |
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tangxifan
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094b3e9b90
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[Script] Use parameters in template yosys script supporting BRAMs
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2021-03-16 19:51:48 -06:00 |
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tangxifan
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cea43c2c45
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[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage
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2021-03-16 18:04:31 -06:00 |
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tangxifan
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73b06256d0
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[Test] Deploy the new yosys script supporting BRAM to regression tests
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2021-03-16 16:52:59 -06:00 |
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tangxifan
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84778bd38d
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[Script] Add new yosys script to support architectures with BRAMs
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2021-03-16 16:52:18 -06:00 |
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tangxifan
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090f483a11
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[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
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2021-03-16 16:45:57 -06:00 |
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tangxifan
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76837e02e6
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[Script] Rename yosys script supporting bram and restructure techlib files
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2021-03-16 16:16:53 -06:00 |
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tangxifan
|
e61857aa2b
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Merge branch 'master' into ganesh_dev
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2021-03-11 19:17:02 -07:00 |
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tangxifan
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366bec232c
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[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
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2021-03-11 15:25:48 -07:00 |
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tangxifan
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bb2a02c9ad
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[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v]
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2021-03-11 15:23:14 -07:00 |
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tangxifan
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baf162e401
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[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification
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2021-03-10 22:45:19 -07:00 |
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tangxifan
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a6186db315
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[Test] Update bitstream annotation with new syntax
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2021-03-10 20:45:17 -07:00 |
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tangxifan
|
7d07f5d8cb
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[Test] Update bitstream setting example with mode bit overwriting
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2021-03-10 15:34:53 -07:00 |
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tangxifan
|
b42541d84e
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[Flow] Support multiple iterations in rewriting yosys scripts
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2021-03-10 14:10:35 -07:00 |
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tangxifan
|
90a00da1df
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[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'
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2021-03-10 13:56:35 -07:00 |
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tangxifan
|
d21909ad6c
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[Test] Use custom rewriting script in lut_adder test
|
2021-03-10 13:48:20 -07:00 |
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tangxifan
|
0e772bc3b4
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[Script] Patch the yosys rewrite script to avoid existing blif outputs
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2021-03-10 13:47:30 -07:00 |
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tangxifan
|
7adb78b159
|
[Script] Add a template yosys script with rewriting at the end
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2021-03-10 13:40:31 -07:00 |
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tangxifan
|
035043d0d8
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[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
|
2021-03-10 13:36:11 -07:00 |
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tangxifan
|
5d46537b5b
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[Script] Allow users to specify custom post-synthesis verilog for simulation
|
2021-03-10 11:45:55 -07:00 |
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tangxifan
|
aafd87c3f9
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[Flow] Update flow-run to support custom yosys rewrite scripts
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2021-03-10 11:36:29 -07:00 |
Tarachand Pagarani
|
db8ea86b2f
|
update tests to use no_ff_map and remove tests that need async set/reset for now
|
2021-03-10 10:04:45 -08:00 |
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Tarachand Pagarani
|
608bd1f658
|
comment out desings that utilize local async reset/preset
|
2021-03-09 19:24:01 -08:00 |
|
Tarachand Pagarani
|
7f4c20ff33
|
comment out desings that utilize local async reset/preset
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2021-03-09 10:37:06 -08:00 |
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Tarachand Pagarani
|
c4b83aeaa9
|
bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type
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2021-03-09 00:46:40 -08:00 |
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tangxifan
|
2daa770319
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[Arch] Update openfpga architecture to include quicklogic cell sim
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2021-03-08 21:40:29 -07:00 |
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tangxifan
|
812d8c950e
|
[Script] Update quicklogic's script to output correct verilog file name
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2021-03-08 21:39:44 -07:00 |
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tangxifan
|
37aa42d305
|
[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
|
2021-03-08 21:38:51 -07:00 |
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tangxifan
|
c53c41b7a5
|
[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file
|
2021-03-08 21:09:23 -07:00 |
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tangxifan
|
131643dcc0
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[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
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2021-03-08 21:08:55 -07:00 |
ganeshgore
|
b860722893
|
Fixed parameter ys_rewrite_params name bug
|
2021-03-08 10:34:39 -07:00 |
|
ganeshgore
|
52de55e7eb
|
Merge branch 'master' into ganesh_dev
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2021-03-08 10:15:06 -07:00 |
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tangxifan
|
906d2fa72d
|
Merge branch 'master' into shift_reg
|
2021-03-08 09:24:29 -07:00 |
|
Ganesh Gore
|
7a35811430
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[Flow] Yosys rewrite support
|
2021-03-08 00:35:47 -07:00 |
|
Ganesh Gore
|
67cd9a69b7
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[Flow] Extended yosys variable subtitution
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2021-03-08 00:21:07 -07:00 |
Lalit Sharma
|
7945628307
|
Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
|
2021-03-07 22:25:01 -08:00 |
|
Lalit Sharma
|
6a1ce01084
|
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
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2021-03-07 22:02:11 -08:00 |
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Tarachand Pagarani
|
ce76c58422
|
add shift register test case
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2021-03-05 09:06:05 -08:00 |
|
Lalit Sharma
|
2b2acae757
|
Adding command to generate verilog file out of yosys run
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2021-03-05 04:07:02 -08:00 |