tangxifan
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b7da22501c
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[Test] Deply new test to regression test
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2021-04-24 15:55:05 -06:00 |
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tangxifan
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5adffad602
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[Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!!
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2021-04-24 15:49:53 -06:00 |
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tangxifan
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80f98328df
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[Test] Update test settings for architecture with fracturable DSP blocks
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2021-04-24 15:16:50 -06:00 |
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tangxifan
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8b8096f3a8
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[HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block
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2021-04-24 14:57:09 -06:00 |
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tangxifan
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a3a98fa21d
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[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition
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2021-04-24 14:56:10 -06:00 |
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tangxifan
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4f454abfde
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[Arch] Add a new architecture using fracturable 16-bit DSP blocks
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2021-04-24 14:01:42 -06:00 |
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tangxifan
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272d1fffb7
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[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks
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2021-04-24 13:30:46 -06:00 |
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tangxifan
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ddcdb35b28
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[Arch] Bug fix in single-mode 8-bit DSP architectures
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2021-04-24 13:30:03 -06:00 |
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tangxifan
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1c6b9a23d7
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[Test] Add new test for multi-mode 16-bit DSP blocks
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2021-04-24 13:29:29 -06:00 |
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tangxifan
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c44688739d
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[HDL] Add verilog netlist for the fracturable 16-bit multiplier blocks
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2021-04-23 22:12:26 -06:00 |
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tangxifan
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09cc7f0007
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[Script] Enable constant net routing for heterogeneous FPGAs
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2021-04-23 20:44:36 -06:00 |
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tangxifan
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189c94ff19
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[Test] Deploy new mac benchmarks to tests
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2021-04-23 20:44:14 -06:00 |
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tangxifan
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200b6d39a6
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[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit
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2021-04-23 20:36:28 -06:00 |
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tangxifan
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671394ec2c
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[Benchmark] Add microbenchmarks for mac with different sizes for DSP testing
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2021-04-23 20:33:43 -06:00 |
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tangxifan
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cbb7d41b6e
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[Script] Enable constant net routing for VTR benchmarks
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2021-04-23 14:15:13 -06:00 |
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tangxifan
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784713e88a
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[Test] Add golden results for IWLS2005 as a simple QoR check
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2021-04-22 19:27:31 -06:00 |
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tangxifan
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a16896054d
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[Script] Enable constant net routing for iwls benchmarks
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2021-04-22 19:16:32 -06:00 |
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tangxifan
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1dcb8e39a9
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[Test] Unlock more IWLS'2005 benchmarks in testing
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2021-04-22 09:23:33 -06:00 |
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tangxifan
|
61a473e479
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[Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support
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2021-04-21 22:56:19 -06:00 |
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tangxifan
|
5a519390ff
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[HDL] Enriched DFF model in yosys technology library
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2021-04-21 22:49:05 -06:00 |
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tangxifan
|
ce6018e123
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[Arch] Enriched DFF model to support active-low/high FFs
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2021-04-21 22:48:31 -06:00 |
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tangxifan
|
adfea88be2
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[HDL] Rename multi-mode DFF module
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2021-04-21 20:06:03 -06:00 |
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tangxifan
|
62497549b6
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[HDL] Add multi-mode DFF module
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2021-04-21 20:04:40 -06:00 |
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tangxifan
|
3a5c26c6a1
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[Test] Update IWLS test by using new architecture and customize DFF techmap
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2021-04-21 19:51:25 -06:00 |
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tangxifan
|
8cbea6a268
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[HDL] Add technology library for customizable DFF synthesis
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2021-04-21 19:50:51 -06:00 |
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tangxifan
|
3d615e1516
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[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping
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2021-04-21 19:50:07 -06:00 |
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tangxifan
|
9d9840d9b7
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[Arch] Add architecture using multi-mode DFFs
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2021-04-21 19:49:48 -06:00 |
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tangxifan
|
8046b16c15
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[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
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2021-04-21 14:04:34 -06:00 |
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tangxifan
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b203ef7bc2
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[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
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2021-04-21 14:03:51 -06:00 |
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tangxifan
|
2fa370d7d5
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[Test] Patch regression tests for fpga bitstream
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2021-04-19 17:15:14 -06:00 |
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tangxifan
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64163edbe6
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[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
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2021-04-19 16:15:25 -06:00 |
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tangxifan
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578d81b67a
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[Test] Patch task configuration file
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2021-04-19 16:15:00 -06:00 |
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tangxifan
|
18eb5c9de9
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[Test] Deploy new test to CI
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2021-04-19 15:56:41 -06:00 |
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tangxifan
|
5976cc0a1c
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[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
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2021-04-19 15:54:18 -06:00 |
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tangxifan
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7018073e28
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[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
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2021-04-17 15:04:51 -06:00 |
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tangxifan
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da95da933b
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[Test] Add pin constraint file to map reset to correct FPGA pins
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2021-04-17 15:04:26 -06:00 |
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tangxifan
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e3dafe99da
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[Arch] Revert to old version arch due to editing by mistake
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2021-04-16 20:58:32 -06:00 |
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tangxifan
|
c020333512
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Merge branch 'master' into dff_techmap
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2021-04-16 20:54:28 -06:00 |
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tangxifan
|
7172fc9ea1
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[Test] Patch test for architecture using asynchronous DFFs
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2021-04-16 20:48:37 -06:00 |
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tangxifan
|
0a15f366cb
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[HDL] Patch dff models used in yosys tech map
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2021-04-16 20:48:15 -06:00 |
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tangxifan
|
16e02ef485
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[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
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2021-04-16 20:47:39 -06:00 |
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tangxifan
|
1c2f91b7e6
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[Script] Patch yosys script with dff tech map
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2021-04-16 20:47:18 -06:00 |
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tangxifan
|
2666726f36
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[Script] Remove clock routing from example openfpga shell script without ace
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2021-04-16 20:46:49 -06:00 |
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tangxifan
|
23d08757cf
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[Script] Add example script without using ACE2
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2021-04-16 20:20:10 -06:00 |
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tangxifan
|
bbdc0e53af
|
[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
|
2021-04-16 20:14:48 -06:00 |
|
tangxifan
|
b11d03f9c5
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[Test] Deploy new test to CI
|
2021-04-16 20:01:40 -06:00 |
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tangxifan
|
93be81abe1
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[Test] Add test case for architecture using DFF with reset
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2021-04-16 20:00:48 -06:00 |
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tangxifan
|
5414a6a3da
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[Script] Add yosys script with custom DFF tech mapping
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2021-04-16 20:00:30 -06:00 |
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tangxifan
|
4239bb4e68
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[Arch] Patch architecture files using multi-mode DFFs
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2021-04-16 19:59:55 -06:00 |
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tangxifan
|
f2f7f010ea
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[Arch] Add new architectures using DFF with reset in VPR
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2021-04-16 19:26:18 -06:00 |