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1511 Commits

Author SHA1 Message Date
tangxifan 9bc9b61d35 [test] fixed a few bugs 2022-09-29 15:11:30 -07:00
tangxifan f5e7ec4dd1 [test] add a new test case to validate wire lut case 2022-09-29 14:28:59 -07:00
tangxifan df1ae7ba2a [benchmark] add a new benchmark to enhance the tests for wire-lut features in repacker 2022-09-29 14:23:17 -07:00
tangxifan f7a02422b5 [arch] add a new arch to reproduce the wire-lut bug in repacker 2022-09-29 13:59:08 -07:00
tangxifan 3f8e2ade2e [script] update missing scripts required by pb_pin_fixup test cases 2022-09-29 13:39:46 -07:00
tangxifan 49fa783914 [script] now suggest to skip pb_pin_fixup step in example scripts for most test cases 2022-09-29 10:45:27 -07:00
tangxifan 79b260f5e1 [arch] update missing arch 2022-09-21 16:52:32 -07:00
tangxifan b1f8cdab3c [test] update missing arch files which are not placed in the openfpga_flow/vpr_arch 2022-09-21 15:28:56 -07:00
tangxifan eaa0b5588a [test] fixed a bug in pin constrain examples 2022-09-21 14:10:12 -07:00
tangxifan b532bca9d2 [script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment 2022-09-21 10:54:16 -07:00
tangxifan baac236ed7 [test] fixed a bug in example scripts due to the changes on vpr options 2022-09-21 10:52:49 -07:00
tangxifan d0b018ad6e [script] mismatches in vpr options due to upgrade 2022-09-21 09:27:26 -07:00
tangxifan 40edf859e3 Merge branch 'vtr_upgrade' of github.com:lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-20 22:38:06 -07:00
tangxifan 97f0445787 [arch] upgrade arch file which was designed for v1.1 2022-09-20 22:37:35 -07:00
tangxifan 36603f9772
Merge branch 'master' into vtr_upgrade 2022-09-20 21:08:06 -07:00
tangxifan e0f632cc9c [test] fixed a bug 2022-09-20 20:29:34 -07:00
tangxifan 645d8df7b9 [test] fixed a bug 2022-09-20 20:09:41 -07:00
tangxifan 9042fc2422 [test] now reg test should show diff details when failed 2022-09-20 19:32:34 -07:00
tangxifan b8f1520367 [test] fixed a bug 2022-09-20 18:12:23 -07:00
tangxifan 4e254a304d [test] now golden netlists have no relationship with OPENFPGA_PATH 2022-09-20 18:10:52 -07:00
tangxifan 5e23be19a5 [test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths 2022-09-20 18:07:31 -07:00
tangxifan 1b0b50b928 [test] update golden netlist 2022-09-20 16:04:05 -07:00
tangxifan a137f7148c [arch] fixed a bug 2022-09-20 15:47:15 -07:00
tangxifan da157ed5de [test] debugging git-diff 2022-09-20 15:31:39 -07:00
tangxifan 3f8106f12e [arch] fixed a bug in the custom I/O location assignment: no more I/Os on the corner of centre fabric 2022-09-20 15:19:32 -07:00
tangxifan b630d60b7e [test] update arch bitstream and force a pin placement for the test case where external bistream is fixed 2022-09-20 14:14:18 -07:00
tangxifan 6a896a9845 [test] debugging 2022-09-20 14:08:22 -07:00
tangxifan ecfdc4a83a [test] debugging 2022-09-20 13:51:32 -07:00
tangxifan abee802830 [script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers 2022-09-20 13:46:30 -07:00
tangxifan bdcdc7d294 [test] Now git diff in basic regression tests should capture the changes on golden outputs 2022-09-20 13:36:31 -07:00
tangxifan 37c5056d6a [test] now use a fixed routing channel width for quicklogic tests 2022-09-20 12:25:40 -07:00
tangxifan 846ca26311 [test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks 2022-09-20 12:08:24 -07:00
tangxifan b3449a338f [arch] update out-of-date vpr arch from v1.1 to v1.2 2022-09-20 09:51:43 -07:00
tangxifan 63cb8d589d [test] fixed a typo 2022-09-19 23:14:15 -07:00
tangxifan 40663f956c [test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability 2022-09-19 21:55:15 -07:00
tangxifan d9bd0a6cf3 [test] disable clustering-routing result sync-up when calling vpr in example scripts 2022-09-19 20:52:04 -07:00
tangxifan fca1c82388 [test] disable clustering and routing sync when using VPR 2022-09-19 20:33:35 -07:00
tangxifan 373566416c Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-16 16:47:21 -07:00
tangxifan a8d7b6c2c4 [script] add a python script for users to visualize the I/O sequence 2022-09-16 10:49:10 -07:00
tangxifan a2e22787c2 [test] deploy the new test cases to the basic regression tests 2022-09-16 10:31:15 -07:00
tangxifan 10e86d334a [test] add test cases to validate the various layouts where I/Os are in the center of the grid 2022-09-16 10:29:19 -07:00
tangxifan f2e13e5ea9 [arch] add more flexible layout to test I/O center features 2022-09-16 10:00:08 -07:00
tangxifan ec38b3990f [arch] update to check OpenFPGA I/O indexing 2022-09-14 13:58:12 -07:00
tangxifan 83c89ae1bf [arch] add more corner case to test the custom I/O location feature 2022-09-13 23:05:41 -07:00
tangxifan 330785635d [test] now use a bigger fabric for the test case on custom I/O location 2022-09-13 17:53:33 -07:00
tangxifan a37e270f25 [arch] now custom I/O loc test case cover I/Os in the center of the fabric 2022-09-13 16:57:18 -07:00
tangxifan 1c2192a87d [engine] fixed a few bugs 2022-09-12 16:50:32 -07:00
tangxifan 0d6e4e3979 [test] add a new example for the repack options 2022-09-12 16:21:49 -07:00
tangxifan a3d070ac6f [benchmark] Now the rst_on_lut benchmark has a comb output driven by rst 2022-09-12 10:43:21 -07:00
tangxifan 314f5395b4 [benchmark] fixed a bug which causes yosys failed 2022-09-09 17:04:59 -07:00
tangxifan 91fe27ff66 [test] deploy new test to ci 2022-09-09 17:00:28 -07:00
tangxifan 1ab7590603 [test] added a new test case to 2022-09-09 16:59:06 -07:00
tangxifan cc974a80f7 [arch] added a new architecture to test the local routing architecture where reset is on LUT 2022-09-09 16:48:10 -07:00
tangxifan 7a38c7dd18 [benchmark] add a new benchmark to test reset signal to drive both lut and ff 2022-09-09 16:42:55 -07:00
tangxifan 95d7a17b3c Merge branch 'master' into vtr_upgrade 2022-09-09 14:32:42 -07:00
tangxifan d4523e819c [test] fixed a bug 2022-09-08 16:55:50 -07:00
tangxifan 419a3a1e46 [arch] fixed a bug 2022-09-08 16:53:52 -07:00
tangxifan 122a323668 [arch] fixed bugs 2022-09-08 16:50:33 -07:00
tangxifan d76f3e3b6c [test] fixed the bug 2022-09-08 16:34:23 -07:00
tangxifan 218e6d0a47 [arch] fixed syntax errors 2022-09-08 16:31:52 -07:00
tangxifan a840aeea7a [test] add a new test to validate custom I/O location syntax and deploy to basic regression tests 2022-09-08 16:27:11 -07:00
tangxifan b1fad0b4e5 [arch] add an example architecture to show the use extended syntax 2022-09-08 16:19:21 -07:00
tangxifan 56619f9a47 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-07 15:04:05 -07:00
tangxifan 477e2119d7 [test] remove abs paths in golden outputs without time stamps 2022-09-06 15:24:43 -07:00
tangxifan 93ab992187 [test] update golden outputs without time stamps 2022-09-06 14:59:00 -07:00
tangxifan 561d0a6545 [test] add more test case to track golden outputs for representative fpga sizes 2022-09-06 14:04:23 -07:00
tangxifan 9e1abf5898
Merge branch 'master' into vtr_upgrade 2022-09-01 21:39:14 -07:00
tangxifan c48f750f86 [test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit 2022-09-01 20:10:29 -07:00
tangxifan c691eb0e95
Merge branch 'master' into vtr_upgrade 2022-09-01 15:54:14 -07:00
tangxifan 51dc082bd4 [test] force a fixed routing chan W for no time stamp test case 2022-09-01 15:02:40 -07:00
tangxifan d86eb04c5d [test] now no timestamp test case covers gsb files 2022-09-01 14:03:51 -07:00
tangxifan 71ad0721a1
Merge branch 'master' into vtr_upgrade 2022-08-31 13:56:17 -07:00
tangxifan 201bca8968 [test] typo 2022-08-30 08:59:20 -07:00
tangxifan 5f88b9a226 [test] typo 2022-08-29 22:41:15 -07:00
tangxifan 0b5bdcdbb1 [test] deploy new test to basic regression tests 2022-08-29 22:07:56 -07:00
tangxifan 069e2b00b1 [test] add more test cases to validate gsb options 2022-08-29 22:03:06 -07:00
tangxifan dbacee8a0a [script] turn off equivalent for soft adder architecture as we do not expect any routing optimization 2022-08-27 20:25:50 -07:00
tangxifan ef3381a1b2 [script] also turn off pb_pin_fixup in vpr for quicklogic tests 2022-08-27 20:07:49 -07:00
tangxifan b9fade4c76 [script] turn off the pb_pin_fix_up in vpr run for mcnc and vtr benchmarks 2022-08-27 20:04:29 -07:00
tangxifan e9d6e7e38a [engine] update vtr and enable more debugging info 2022-08-27 19:12:43 -07:00
tangxifan 8d6682c28b [test] fixed a bug when removing previous runs 2022-08-25 16:20:18 -07:00
tangxifan fa790d50d4 [script] fixed a bug on wrong path to the ace2 executable 2022-08-23 10:53:44 -07:00
tangxifan bdb051f787 [arch] update arch files 2022-08-22 18:24:37 -07:00
tangxifan 6c44f321e5 [script] fixed a bug 2022-08-22 18:24:26 -07:00
tangxifan 2bbf2f02c9 [script] now return status on each arch upgrade task 2022-08-22 18:23:00 -07:00
tangxifan b6e1175517 [script] update doc and avoid modify README.MD when updating arch files 2022-08-22 18:19:23 -07:00
tangxifan 8d45903dc2 [script] makefile for vpr arch 2022-08-22 18:13:48 -07:00
tangxifan 3c9c11d451 [script] working on formatting 2022-08-22 18:02:38 -07:00
tangxifan 55e765a206 [script] slight improve on formatting 2022-08-22 18:00:14 -07:00
tangxifan 4a7c3fce93 [script] debugging format 2022-08-22 17:04:30 -07:00
tangxifan 2f5ea0cabb [script] functional arch file converter; need to clean up formatting issues 2022-08-22 16:40:49 -07:00
tangxifan 4efc506762 [script] now change to use minidom and debugging the child removal 2022-08-22 16:33:49 -07:00
tangxifan 880d7122bf [script] complete code; start debugging on arch file converter 2022-08-22 12:29:49 -07:00
tangxifan 5134ea2233 [script] save progress 2022-08-22 11:00:46 -07:00
tangxifan a61d6a2685 [script] developing arch converting script 2022-08-22 10:34:29 -07:00
tangxifan c0b1d76a5e [script] change default tool paths for OpenFPGA flow scripts 2022-08-18 11:02:21 -07:00
tangxifan 6ce1d4804c [test] deploy new test case to basic regression tests 2022-08-01 21:05:05 -07:00
tangxifan 9ea4a7c90f [script] fixed a bug 2022-08-01 19:18:41 -07:00
tangxifan 8b17bf1b1c [test] add a new test case to validate that .act file is not required when power analysis flow is off 2022-08-01 18:44:47 -07:00
tangxifan 55c7b75ab6 [script] even when power analysis mode is turned off, if users define a act file, still use it 2022-08-01 18:13:57 -07:00
root 0da44ad1fc [script] now .act file is no longer required in openfpga_flow/task when power analysis option is off 2022-08-02 08:02:28 +08:00
tangxifan 35fe858035 [test] fixed a few bugs 2022-07-28 12:06:16 -07:00
tangxifan ca9122ddb9 [test] fixed a bug 2022-07-28 11:57:47 -07:00
tangxifan ec31e124b7 [test] reworked test case on pcf2place 2022-07-28 11:51:56 -07:00
tangxifan 23f98d6a3b [engine] fixed a few bugs 2022-07-26 13:55:29 -07:00
tangxifan 353de4546f [test] add 'write_fabric_io_info' command to test cases 2022-07-26 13:48:54 -07:00
taoli4rs 347a29f27c Fix test name in basic regression test script. 2022-07-20 21:05:31 -07:00
taoli4rs 3762a3aae4 Code clean up based on review. 2022-07-20 14:34:44 -07:00
taoli4rs cfc0d08060 Add constrain_pin_location command in openfpga; add full flow test. 2022-07-20 11:51:00 -07:00
tangxifan 4b9431b132 [test] avoid XML bitstream output when can go beyond github runners' disk space 2022-05-25 18:45:26 +08:00
tangxifan 9832722056 [test] now add QuickLogic memory bank to fpga bitstream regression tests 2022-05-25 11:42:32 +08:00
tangxifan 86347a9d49 [test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols 2022-05-25 11:19:49 +08:00
tangxifan 7d694acf32 [test] debugging basic reg test paths 2022-05-23 11:21:36 +08:00
tangxifan b41cbad5d3 [test] force to run git diff under root directory 2022-05-23 10:32:43 +08:00
tangxifan 488a934097 [test] give abs path for git diff in basic regression tests 2022-05-23 09:12:33 +08:00
tangxifan 0dc7caf3b7 [test] now regression test script supports remove all run dir through command-line options 2022-05-22 13:15:39 +08:00
tangxifan 751d87b8e3 [test] fix a bug in detect changes in golden netlists 2022-05-22 13:06:47 +08:00
tangxifan 6719a9aa26 [test] update golden netlists/testbenches etc. 2022-05-22 13:03:01 +08:00
ganeshgore 17c4e9a1bb
Merge branch 'master' into binder 2022-05-10 19:58:17 -06:00
tangxifan d7e854eae7 [test] deploy new test to ci 2022-05-09 17:23:57 +08:00
tangxifan 7ed1548c6e [arch] fixed a few bugs 2022-05-09 17:22:48 +08:00
tangxifan 9f56e61342 [arch] syntax 2022-05-09 17:13:57 +08:00
tangxifan 0afe3a6d33 [HDL] update dff map rules to support negative triggered ffs 2022-05-09 16:58:18 +08:00
tangxifan 22c4d72358 [test] add a test case to validate negative edge-triggered ff 2022-05-09 16:57:42 +08:00
tangxifan 9c7868cfab [hdl] add a counter design which is triggered by negative edges 2022-05-09 16:41:21 +08:00
tangxifan 812af4f722 [arch] add arch that supports negative edge triggered flip-flop 2022-05-09 16:32:01 +08:00
tangxifan c8ff3fc8dc [test] add regression test to validate compilation of openfpga cell library files 2022-05-09 16:00:51 +08:00
tangxifan d4992fd9ad [HDL] Add a multi-mode ff which can support posedge and negedge 2022-05-09 15:52:17 +08:00
Ganesh Gore daae02a614 Minor documentation update 2022-05-08 13:03:16 -06:00
Ganesh Gore 522982c9ba Adde vtr_benchmarks_template for demo 2022-05-06 22:40:36 -06:00
Ganesh Gore 9473523b6b Added VTR arch without fracturable lut 2022-05-06 11:05:16 -06:00
Ganesh Gore 275cda081e [Bugfix] Typo 2022-05-05 08:40:21 -06:00
Ganesh Gore e845b62322 Update regession tasks 2022-05-05 01:46:19 -06:00
Ganesh Gore 1e243650b9 Added option to copy example projects 2022-05-03 14:06:16 -06:00
Ganesh Gore 21c3dbf611 Added regression for template project 2022-05-02 23:23:45 -06:00
Ganesh Gore 9891e42f7a Added template task 2022-05-02 11:49:16 -06:00
tangxifan 9bd66d531e [Test] Deploy the new test case to basic regression tests 2022-04-13 16:06:27 +08:00
tangxifan efc25aa66e [Script] Fixed a bug in wrong paths 2022-04-13 16:04:33 +08:00
tangxifan 5beefda3bd [Test] Add a new test case to validate the fix_pins option 2022-04-13 15:55:21 +08:00
tangxifan 576b9c2d8f [Script] Disable SDC writer in multiclock examples 2022-03-20 11:05:29 +08:00
tangxifan 3e3a65223c [Test] Deploy new test case to basic regression tests 2022-03-20 11:04:07 +08:00
tangxifan f8845f7d3a [Test] Add a test case to validate separated clock pins in global port 2022-03-20 11:02:07 +08:00
tangxifan c8da85cc24 [Doc] Update naming convention for OpenFPGA architecture files 2022-03-20 10:51:55 +08:00
tangxifan a1e2d9c864 [Arch] Add a new example openfpga arch where clock ports are independent 2022-03-20 10:50:31 +08:00
tangxifan 9f7a182433 [Arch] Typo 2022-02-24 09:51:26 -08:00
tangxifan fdaf97e60d [Test] Update test case by using GPIO with config_done signals 2022-02-24 09:49:34 -08:00
tangxifan fcaff28e24 [HDL] Add a new IO cell with config_done support 2022-02-24 09:46:55 -08:00
tangxifan a615c9d4e3 [Test] Rename test cases 2022-02-24 09:43:41 -08:00
tangxifan e443a4567d [Arch] Typo 2022-02-23 22:09:26 -08:00
tangxifan b27a04eb24 [Test] Now test case has a config done CCFF 2022-02-23 22:07:11 -08:00