Commit Graph

385 Commits

Author SHA1 Message Date
tangxifan f687774452 bug fix in template scripts 2020-07-26 21:46:03 -06:00
tangxifan 41a76126b9 add fabric bitstream writer to CI 2020-07-26 21:44:42 -06:00
tangxifan c87f6b75b9 add test case for FPGA-SPICE 2020-07-24 19:12:35 -06:00
tangxifan 020154b0cd add depopulate crossbar test case 2020-07-24 18:06:02 -06:00
tangxifan 021fedbc12 update fabric key to synchronize with new module/instance naming 2020-07-24 12:55:40 -06:00
tangxifan fefcd88f14 update openfpga architecture README for power-gating 2020-07-22 21:55:59 -06:00
tangxifan 22159531c5 bug fix in power gating support of FPGA-Verilog 2020-07-22 20:21:38 -06:00
tangxifan ca867ea6fa add power gate inverter test case (full testbench) 2020-07-22 20:09:52 -06:00
tangxifan 87ef7f9f99 add power gate example architecture 2020-07-22 20:06:10 -06:00
tangxifan 8ade40713a add missing architecture for CI 2020-07-22 14:07:39 -06:00
tangxifan 1a1c3885e7 use k6 n10 in mux designs to speed up CI 2020-07-22 13:54:09 -06:00
tangxifan 95c1fe61e1 use k6 n8 in mux design to speed up CI 2020-07-22 13:49:03 -06:00
tangxifan f754c8af06 use k6_n10 architecture to reduce CI runtime 2020-07-22 13:45:55 -06:00
tangxifan 92c3449999 bug fix in the regression test due to benchmark changes 2020-07-22 13:17:05 -06:00
tangxifan 05dccadf21 bug fix in the testcases using yosys_vpr flow 2020-07-22 12:44:19 -06:00
tangxifan 7d39e136a4 enrich micro benchmarks 2020-07-22 12:33:52 -06:00
tangxifan 1d36de817f adapt generate bitstream testcase to use yosys vpr flow 2020-07-22 12:24:34 -06:00
tangxifan b96cdbf857 adapt preconfig test cases to use yosys_vpr flow 2020-07-22 12:23:39 -06:00
tangxifan d8804f4ec1 deploy yosys_vpr flow to basic regression tests 2020-07-22 12:21:59 -06:00
tangxifan f4e77e3bad Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2020-07-22 12:09:34 -06:00
ganeshgore 3b6cd885f3 BugFix: Fixed yosys_vpr with openFPGA_Shell 2020-07-22 11:57:04 -06:00
tangxifan eb070694b5 fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture 2020-07-15 17:52:41 -06:00
tangxifan ca90f337a7 add fast configuration chain test case 2020-07-15 11:56:47 -06:00
tangxifan 66a50742fc use configuration chain in the k4k4 test case to speed up CI 2020-07-15 11:56:11 -06:00
tangxifan 1c5bede282 update arch file with device technology binding information 2020-07-13 19:06:51 -06:00
tangxifan 824b56f14c fabric key can now accept instance name only; decoders are no longer part of the key 2020-07-06 16:42:33 -06:00
tangxifan 1e6955aaa4 rename arch directory to be clear for its usage 2020-07-04 19:13:28 -06:00
tangxifan f9a2bb0490 Reorganize task directory 2020-07-04 19:06:41 -06:00
tangxifan 4f8260a7ba remove obselete codes and update regression tests 2020-07-04 17:31:34 -06:00
tangxifan 1c634e4600 add missing task file for generate bitstream test case 2020-07-02 17:24:51 -06:00
tangxifan adea6fcec4 add bitstream generation only test case to CI 2020-07-02 16:31:22 -06:00
tangxifan 73e75bf456 add readme for OpenFPGA architecture naming 2020-07-01 10:27:21 -06:00
tangxifan 20cf4acda0 add readme for architecture file naming 2020-07-01 09:54:13 -06:00
tangxifan b2fb5f760c update sample key 2020-06-27 15:01:12 -06:00
tangxifan d526f08782 deploy bitstream reader in openfpga shell 2020-06-20 18:48:19 -06:00
tangxifan 3d56cd3060 fine tuning on the script for MCNC benchmarks 2020-06-15 20:09:46 -06:00
tangxifan 0d81f60fd8 add new options to openfpga task configuration files 2020-06-12 19:48:39 -06:00
ganeshgore 559564c333 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2020-06-12 17:31:14 -06:00
ganeshgore 41585436c8 Added external_fabric_key_file key 2020-06-12 15:37:12 -06:00
tangxifan 2d35848cfa add external key test cases 2020-06-12 13:11:21 -06:00
tangxifan 65b387a589 develop test cases for fabric keys 2020-06-12 11:32:52 -06:00
tangxifan cf9c3b0f44 add write fabric to test cases 2020-06-12 10:50:23 -06:00
tangxifan 60dd37e086 remove simulation settings from openfpga arch XML
update travis to split CI tests

fix errors in travis configuration

fixing travis errors in scripts

keep fixing travis

fix travis on build.sh

bug fixing in travis CI

bug fix in travis regression test run

fixing bugs in the travis scripts

bug fix in travis script: remove common.sh in regression test call

keep bug fixing in travis
2020-06-11 19:31:17 -06:00
tangxifan 068d9943e7 update all the templates and regression test cases with simulation settings 2020-06-11 19:31:16 -06:00
tangxifan 1842bf51e1 deploy read_openfpga_simulation_setting in CI on a single test case 2020-06-11 19:31:16 -06:00
tangxifan cb09896f23 add example simulation setting for openfpga flow 2020-06-11 19:31:15 -06:00
tangxifan 96b58dfdbb use new simulation setting command in openfpga shell 2020-06-11 19:31:15 -06:00
tangxifan c87dbc4880 start using counter benchmark in regression tests 2020-06-11 19:31:15 -06:00
tangxifan f73dfa2bcc bug fixed in k6_n10_40 architecture 2020-06-11 19:31:15 -06:00
tangxifan baa2c6b7ef update arch to support reset signal for SRAm 2020-06-11 19:31:14 -06:00
tangxifan aac2e8c805 update openfpga architecture for memory bank usage 2020-06-11 19:31:14 -06:00
tangxifan 82b04ae3f0 add SRAM verilog for memory bank usage 2020-06-11 19:31:14 -06:00
tangxifan 3f9afea3e8 add preconfig testbench test case for memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 288294c23a add fast configuration test case for memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 73d4c835b7 add regression test case for memory bank 2020-06-11 19:31:13 -06:00
tangxifan a1ec6833c2 add memory bank example arch xml 2020-06-11 19:31:13 -06:00
tangxifan 2def059b5b add standalone configuration protocol to pre config test cases 2020-06-11 19:31:12 -06:00
tangxifan 5f6a790eff add new test cases for the standalone memory configuration protocol 2020-06-11 19:31:12 -06:00
tangxifan 8b5b221a21 add new architecture for standalone memory organization 2020-06-11 19:31:12 -06:00
tangxifan a5138113e4 add fast configuration testcase 2020-06-11 19:31:12 -06:00
tangxifan 8b3e79766c add fast configuration option to fpga_verilog to speed up full testbench simulation 2020-06-11 19:31:12 -06:00
tangxifan 05aa166a9e add preconfig testbench cases to regression tests for different configuration protocols 2020-06-11 19:31:11 -06:00
tangxifan 827e2e6713 file moving in regression tests 2020-06-11 19:31:11 -06:00
tangxifan b5e5182f52 frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops 2020-06-11 19:31:11 -06:00
tangxifan 583c15131b change configuration latch to be triggered at negative edge; Frame-based fabric passed Modelsim verification but failed in iVerilog 2020-06-11 19:31:11 -06:00
tangxifan 6a72c66eb8 bug fixed for frame-based configuration memory in top-level full testbench 2020-06-11 19:31:11 -06:00
tangxifan f5968fda52 add configurable latch Verilog codes 2020-06-11 19:31:10 -06:00
tangxifan 1e73fd6def create configuration frame example script 2020-06-11 19:31:10 -06:00
tangxifan 3a0d3b4e95 fix the broken CI/regression tests due to incorrect file path 2020-06-11 19:31:10 -06:00
tangxifan 3fa3b17061 start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches. 2020-06-11 19:31:10 -06:00
tangxifan bba476fef4 add explicit port mapping support to Verilog testbench generator 2020-06-11 19:31:07 -06:00
tangxifan 910be3cadb massively deploy disable_timing for configure ports in CI 2020-06-11 19:31:06 -06:00
tangxifan 13f591cacf add new command to disable timing for configure ports of programmable modules 2020-06-11 19:31:06 -06:00
tangxifan fc2b09514e add configuration chain write to regression tests 2020-06-11 19:31:06 -06:00
tangxifan 1943929353 add write_fabric_hierarchy to regression tests 2020-06-11 19:31:04 -06:00
tangxifan 98fbcb5410 add time unit test for SDC generation to CI 2020-06-11 19:31:04 -06:00
tangxifan 4083fae41a add new test cases about user-defined simulation settings 2020-06-11 19:31:03 -06:00
tangxifan 2fbf9c2cfc change to a higher simulation clock speed to accelerate CI verification.
Later, we should place simulation information in another XML so that we can reuse that easily
2020-06-11 19:31:03 -06:00
tangxifan 889bc8dbe8 add more test cases about LUT design and deploy to CI 2020-06-11 19:31:02 -06:00
tangxifan 889f179ce7 add local encoder test case 2020-06-11 19:31:01 -06:00
tangxifan 98a658a013 bug fixed in routing_test.v. Deployed to regression tests 2020-06-11 19:31:01 -06:00
tangxifan 6dd8d347e1 try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif 2020-06-11 19:31:01 -06:00
CHARAS SAMY f6cea1e17c Added test_mode_low benchmark 2020-06-11 19:31:01 -06:00
CHARAS SAMY 3c781b18d3 Added routing benchmark 2020-06-11 19:31:01 -06:00
tangxifan 42cede37fa add testcases on generate fabric/testbench only 2020-06-11 19:31:01 -06:00
tangxifan 9bf91bd92a start testing mcnc_big20 using OpenFPGA tasks 2020-06-11 19:30:55 -06:00
ganeshgore c31b20dc91 Added support for simulation setting file in the task flow 2020-06-11 19:28:13 -06:00
ganeshgore 49edeb119c BugFix : Relative path for refrence benchmark fixed 2020-06-11 19:28:13 -06:00
ganeshgore 890ead91b9 Fixed modelsim include references 2020-06-11 19:28:13 -06:00
ganeshgore c1b73efa62 Added support for simulation setting file in the task flow 2020-06-10 23:12:30 -06:00
ganeshgore a3103f6afe BugFix : Relative path for refrence benchmark fixed 2020-04-25 20:16:17 -06:00
ganeshgore 9d1b3d6865 Fixed modelsim include references 2020-04-24 21:53:57 -06:00
tangxifan 90f608baea changing task mcnc file for debugging (temporarily now) Will be corrected later 2020-04-23 18:58:39 -06:00
tangxifan 417d534121 fine tune mcnc example script to run Modelsim simulations easily 2020-04-23 16:15:45 -06:00
tangxifan df85175765 fine tuning on mcnc example script so that we can run run_modelsim.py --runsim 2020-04-22 21:44:52 -06:00
tangxifan f9fcc6b471 tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation 2020-04-22 18:24:09 -06:00
tangxifan 726185cd5e add test cases using spypad architecture 2020-04-22 12:56:57 -06:00
tangxifan 73e9006372 add arch file with spy pads 2020-04-22 12:56:09 -06:00
tangxifan 9fb8971281 add FPGA arch with spypads to portofilo 2020-04-22 11:12:28 -06:00
tangxifan 9761d13eef update microbenchmark and2 module name 2020-04-20 13:37:39 -06:00
tangxifan 489ca75230 adapt benchmark and_latch module name to be different than benchmark and 2020-04-20 13:15:05 -06:00
tangxifan f6b7583a2a add tasks for single mode 2020-04-20 12:55:40 -06:00
tangxifan 8b03ec900f fine-tune micro benchmark to fit port mapping in testbenches 2020-04-19 17:05:12 -06:00
tangxifan e10cafe0a5 Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
2020-04-19 16:42:31 -06:00
tangxifan 32ed609238 update micro benchmark set and regression tests using them 2020-04-19 12:49:07 -06:00
tangxifan 98878f474b light change on arch file to accelerate mcnc big20 run 2020-04-19 12:03:31 -06:00
tangxifan cc163081f5 recover mcnc big20 test configuration 2020-04-18 21:06:43 -06:00
tangxifan 2e3a811f4f critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results 2020-04-18 21:04:46 -06:00
tangxifan f76a3090c4 add mcnc big20 test cases and start debugging 2020-04-18 19:25:16 -06:00
tangxifan 95863e996a minor update on arch to use auto layout sizing 2020-04-18 18:43:56 -06:00
tangxifan 2f3a36ee81 update timing and rename the arch file 2020-04-18 18:39:47 -06:00
tangxifan 7ce34be175 update sample architecture timing 2020-04-17 22:06:06 -06:00
tangxifan 2ea4b8a2a2 add more flagship architectures 2020-04-17 19:12:27 -06:00
tangxifan 2ffd174e6a fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI 2020-04-15 15:48:33 -06:00
tangxifan 032ebc29e6 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2020-04-15 12:53:20 -06:00
tangxifan 1e742a3676 add test case on auto-check test benches 2020-04-15 12:52:52 -06:00
ganeshgore 689c4a3e19 BugFix: The filename in the previous commit 2020-04-15 12:44:22 -06:00
tangxifan 46fe1e84ce Merge branch 'dev' into ganesh_dev 2020-04-15 12:27:51 -06:00
ganeshgore 7f37bf1441 Added formal verification support to fpga_flow script 2020-04-15 12:24:51 -06:00
tangxifan 7ba3e27371 add duplicated_grid_pin test case to Travis CI 2020-04-12 20:10:51 -06:00
tangxifan e78643f108 add flatten routing test case to Travis CI 2020-04-12 20:06:40 -06:00
tangxifan 59ea0a6ad5 add implicit verilog test case to Travis CI 2020-04-12 20:00:20 -06:00
tangxifan 23aef96d3a add behavioral verilog test case to Travis CI 2020-04-12 19:55:47 -06:00
tangxifan 11e9014542 add notes about debugging the aib FPGA 2020-04-12 19:07:53 -06:00
tangxifan a614e5aad9 add long adder chain to Travis CI 2020-04-12 15:43:19 -06:00
tangxifan f71a85a1d4 add test cases on different routing multiplexer circuit designs to Travis CI 2020-04-12 15:39:45 -06:00
tangxifan 214d98fbcd add register chain and scan chain to Travis CI 2020-04-12 15:28:22 -06:00
tangxifan 148cc74d6a add io test cases to Travis CI 2020-04-12 15:01:47 -06:00
tangxifan da5af8f0e0 try to add aib test case. bug found 2020-04-12 14:54:45 -06:00
tangxifan 28cb412359 add test case of wide BRAM 16k to Travis CI 2020-04-12 14:37:08 -06:00
tangxifan 5d665aa04b reshape bram test case 2020-04-12 14:32:09 -06:00
tangxifan 600a48edc7 add test case of BRAM to Travis CI 2020-04-12 14:27:05 -06:00
tangxifan 2444752de8 add untileable test case to Travis CI 2020-04-12 14:08:24 -06:00
tangxifan d806ad3148 add testcases using openfpga_shell in openfpga_flow 2020-04-12 12:54:21 -06:00
tangxifan 68fd296e14 add more test vpr architecture to regression tests 2020-04-12 12:49:16 -06:00
ganeshgore 80bdb41df6 Updated task file to run formal verification 2020-04-11 18:30:21 -06:00
tangxifan 49ddbf98c3 add more testing architecture to openfpga_flow 2020-04-11 18:01:09 -06:00
tangxifan 130b78ca74 update arch in openfpga_flow 2020-04-11 18:00:37 -06:00
ganeshgore f6b3c5854a Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
2020-04-11 16:45:22 -06:00
ganeshgore 8ea272dc2c Patched the OpenFPGA shell execution bug 2020-04-08 21:28:14 -06:00
ganeshgore 583a4d8767 Fixed bug in openfpga_flow script 2020-04-08 12:04:08 -06:00
ganeshgore e1db4df744 Created task for FPGA shell run 2020-04-06 00:35:07 -06:00
ganeshgore ea4122a8a4 Updated openfpga_flow and task file to support sheel run 2020-04-06 00:34:36 -06:00
ganeshgore 7f98ecc8a6 OpenFPGA shell run test script template 2020-04-06 00:32:43 -06:00
ganeshgore eb3b02277a Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
ganeshgore 77f7e13ba7 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2020-04-05 20:59:10 -06:00
ganeshgore d1d3446568 backedup partial upgrade for fpga_flow script 2020-04-05 11:36:24 -06:00
tangxifan 2f38b5cbc2 Merge branch 'refactoring' into dev 2020-03-08 16:23:20 -06:00
tangxifan b219b096ee hotfix on removing dangling inputs from GSB, which are CLB direct output 2020-03-08 13:54:49 -06:00
AurelienUoU c51001c853 Add compilation verification task in openfpga_flow 2020-01-23 13:13:23 -07:00