adf7dd7b5e
Merge branch 'riscv' into riscv-compliance
2018-04-12 16:03:54 -07:00
7eca2dfe5d
Squashed commit of the following:
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commit fb7009fc38e09dd6222973b6ea55ebc3bdcb0c4a353cf212bde73d82e3d6f97e4b53e4
2018-04-12 15:02:04 -07:00
1ba3986eb7
More test/SBA RTL debug
2018-04-12 12:26:54 -07:00
a9b8820916
Checkpoint: debugging tests
2018-04-11 18:10:48 -07:00
50cd4203a5
Fix more style issues with previous commit
2018-04-11 14:41:00 -07:00
4191505b76
Fix style issues with previous commit
2018-04-11 14:38:51 -07:00
cc98a14839
Added address alignment test, code fixups from review
2018-04-11 14:26:16 -07:00
1fda89c3ce
Only write hartsel if we're changing it.
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DebugBreakpoint went from 2.94s to 2.74s.
Change-Id: Ia3ab857aea89fb83f0bcdd9a6bb69f256bde13dd
2018-04-09 15:13:24 -07:00
836bd7cb69
Fix sign compare compiler error
2018-04-09 11:55:46 -07:00
c2c52c89b1
Fix some build issues
2018-04-09 11:38:41 -07:00
99f2f5a272
Change #ifdef SIM_ON to be a run-time arg
2018-04-09 11:26:31 -07:00
de329f4004
Fixed style issues in previous commit.
2018-04-09 10:54:21 -07:00
a9b2277574
Add #ifdef to only enable sbbusyerror test in simulation.
2018-04-09 10:51:53 -07:00
238b1e9f06
Cache registers while halted.
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This saves us from re-reading s0 before doing just about anything
program buffer related.
Improves DebugBreakpoint from 3.01s to 2.89s. Feels like the improvement
should be larger than that. Maybe my metric isn't very good.
Change-Id: I85e1a1ddbf09006d76c451a32048be7b773dcfe9
2018-04-06 15:52:40 -07:00
7c6f6d79bc
Fixed more style issues
2018-04-05 17:59:43 -07:00
5c0a9a9ee4
Just read abstractcs once when executing a command
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DebugBreakpoint went from 3.41s to 3.05s!
Change-Id: Icfc4ad5fb663b3607bf2027fda744b43be662fc5
2018-04-05 17:59:07 -07:00
d471fff3db
Fixed build issues
2018-04-05 17:57:53 -07:00
ada78cae11
Checkpoint: fix even more code style issues
2018-04-05 16:49:00 -07:00
8c8bed878c
Checkpoint: fix some more code style issues
2018-04-05 16:42:28 -07:00
761aaeba98
Checkpoint: fix some code style issues
2018-04-05 16:39:33 -07:00
3bdb8b29a8
Checkpoint: finish debug of tests, working on hitting sbbusyerror case
2018-04-05 16:31:09 -07:00
c5a8e1cf4c
Initial commit of tests for SBA feature
2018-04-04 13:50:17 -07:00
6030644a9d
Track misa per-hart even in -rtos mode
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This works around some side effects of the -rtos hack, namely that we
were unable to set hardware breakpoints on harts whose misa differed
from the first one. There may be other bugs like this one lurking
elsewhere. The only proper solution is for gdb to have a better user
interface when talking to a server that exposes multiple targets, but
that's a very big project.
This fixes #194 .
Change-Id: I81aedddeaa922d220e936730e9c731545953ae21
2018-04-03 15:12:19 -07:00
eeae8c4261
Add gdb_report_register_access_error command
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This replaces the earlier mechanism which would propagate errors only
for targets that decided they wanted to. It was suggested by Matthias
Welwarsky from the OpenOCD team.
Change-Id: Ibe8e97644abb47aff26d74b8280377d42615a4d3
2018-04-02 13:37:53 -07:00
755c6a4caa
Add wall clock timeout to dmi_op()
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If the target is held in reset we'd keep adding more delays, and since
those grow exponentially they'd get so huge it would take forever to
exit out of the loop.
Change-Id: Ieaab8b124c101fd1b12f81f905a6de22192ac662
2018-03-30 15:24:16 -07:00
58a2994b00
Merge pull request #231 from riscv/auth
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Fix auth error message.
2018-03-30 14:02:29 -07:00
3c7c7e26a4
Merge pull request #230 from riscv/deleg
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Make m*deleg regs conditional on U/S/N
2018-03-30 14:02:13 -07:00
4ee7d5373d
Fix auth error message.
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Change-Id: I79b72325e9a6b85f8b67df8e9837a54cfce928f0
2018-03-30 13:21:00 -07:00
224e7b4f16
Once more... Less sloppy this time.
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Change-Id: I4a24e777af3a0d8e072bc1bce0b314738393aa86
2018-03-27 11:42:32 -07:00
55e427b72b
Don't rely on havereset when deasserting reset.
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This removes the need for the supports_havereset config option as well.
Change-Id: Ic4391ce8c15d15e2ef662d170d483f336e8e8a5e
2018-03-27 11:31:39 -07:00
0c05aafbf8
Fix m*deleg logic.
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Change-Id: Ieda035280334f8e7dc78c9fbc2bdbea7c565d2de
2018-03-26 16:00:34 -07:00
b6dca68b2e
Make m*deleg regs conditional on U/S/N
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Change-Id: I544fc15625400d8ad64d4a65f0fc9d77f428ca84
2018-03-23 13:43:12 -07:00
c534a37fc3
Make reset work again for multicore
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Both regular multicore and RTOS hack methods.
Change-Id: I9a0998de0f33ef8a4d163f36ddf01c7675893b3d
2018-03-23 12:53:24 -07:00
d7282d0bfe
Add set_supports_havereset
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This lets reset work on targets that don't implement havereset.
Change-Id: I09eb20970fac740eb6465541db6e739ae3e6b0d5
2018-03-22 12:44:15 -07:00
e5591c2584
Halt the target again if it was reset while halted
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Change-Id: I59707e7b2e1646c312d4eb8e96e9d7dfd1e128c2
2018-03-20 12:34:17 -07:00
52eabbd2a5
Add `riscv set_prefer_sba`
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This allows a user to tell OpenOCD to prefer system bus access for
memory access, which can be useful for testing, or when there really is
a difference in behavior.
Change-Id: I8c2f15b89a2ccdae568c68ee743b75a74f9ad6bd
2018-03-19 14:09:56 -07:00
d5b450c508
Fix build, broken by b7c5c5d228.
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Change-Id: Iee55d799e14376ec5079d7db5fc6369e85368212
2018-03-19 12:56:05 -07:00
40e0c5b976
Format error messages.
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Change-Id: I50c21319765e1ead279223466ed02a06ecf6a522
2018-03-19 12:46:10 -07:00
b7c5c5d228
Merge pull request #225 from riscv/old_bus2
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Support v0 System Bus Access
2018-03-19 12:11:28 -07:00
4d2d1f7324
Notice when a hart has reset.
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Attempt to notify the user.
Deal correctly with a halted target that is suddenly running.
Change-Id: Ib0e0aa843d1da22df673713687ec884f6af14949
2018-03-16 15:04:14 -07:00
fd2759a63d
Clear havereset in examine() and deassert_reset().
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Change-Id: I89f32a44ebd6f3df0d0e2f6b54b111daa6ab06f7
2018-03-16 15:03:31 -07:00
848062d0d1
Propagate errors in more places
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Change-Id: I5a7594d4b44c524537827f403348d0c10814546f
2018-03-16 15:03:31 -07:00
3ddbbd525d
Merge pull request #222 from riscv/dmi_commands
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Add riscv dmi_read/dmi_write commands.
2018-03-15 11:32:33 -07:00
68a6812a41
Use TARGET_PRIxADDR instead of PRIx64.
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Change-Id: Iaf71a2d767ff4876b4cf1c9d546744ec6f97dda2
2018-03-09 18:02:18 -08:00
075610d495
Support v0 system bus access
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This code was submitted at
https://github.com/riscv/riscv-openocd/pull/214 . This change
incorporates that code, makes it build, and fixes the style to fit the
OpenOCD style guide.
I have not tested the new code because I don't have a target. It does
not cause any regressions.
Change-Id: Ic3639d822c887bd4a5517f044855fdd9d4e5a46d
2018-03-09 18:02:18 -08:00
fd9de02fac
Merge pull request #221 from riscv/reg_running
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Error instead of asserting on reg access failure
2018-03-07 12:22:33 -08:00
c10c570dca
Fix cut and paste error message.
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Change-Id: I1ff28278c6fc1b6dda1be53ca4f8ec2dd841b117
2018-03-06 13:22:57 -08:00
ddb894edf6
Add riscv dmi_read/dmi_write commands.
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Mostly addresses #207 .
Also changed dmi_read() to return an error, and fixed all the call sites
to propagate that error if possible.
Change-Id: Ie6fd1f9e7eb46ff92cdb5021a7311ea7334904f1
2018-03-06 12:45:55 -08:00
509e0e4715
Error instead of asserting on reg access failure
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Instead of asserting, return error when an abstract register access
fails on running target.
Fixes #201
Change-Id: I1ab3b31b0a4babf83c44f95ee2eeca92ef906d2f
2018-03-02 20:24:58 -08:00
84c0fdd5d1
Don't always error if a debug program fails
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This is often expected, and the calling code should decide whether to
emit an error or not.
Change-Id: Ic21f38b4c75f01e6b40034fdc60dde6ba7a55f4a
2018-03-02 20:02:32 -08:00
1d00d03dc0
Remove unable to read register error message
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It confuses users of IDEs like Eclipse, which request to read registers
that don't exist on the target.
Fixes #176
Change-Id: Ie2504140bfc70eba0d88fd763aacd87895aa20ff
2018-03-02 19:41:31 -08:00
1d9418fbb0
Only propagate register errors on some targets
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Without this change, connecting to ARM targets is impossible.
Fixes #115 .
Change-Id: Ie33c7e15ac1bed8c9cbd8e6a78de92d5498c5999
2018-03-01 15:11:11 -08:00
0c8235d11f
Merge pull request #216 from kaspar030/fix_some_fallthroughs
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target/riscv: add some switch fallthrough comments
2018-02-28 12:31:22 -08:00
d388f1cbb2
Merge pull request #218 from riscv/auth
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Add `riscv authdata_read` and `riscv authdata_write` commands to support arbitrary authentication through TCL scripts
2018-02-28 09:20:31 -08:00
39716b15ab
Fix authentication for multi-core targets.
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When authdata_write sets the authenticated bit, examine() every OpenOCD
target that is connected to the DM that we were authenticated to.
Change-Id: I542a1e141e2bd23d085e507069a6767e66a196cd
2018-02-27 14:22:06 -08:00
10108b623d
Add `authdata_read` and `authdata_write` commands.
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They can be used to authenticate to a Debug Module.
There's a bit of a chicken and egg problem here, because the RISCV
commands aren't available until the target is initialized, but
initialization involves examine(), which can't interact with the target
until authentication has happened. So to use this you run `init`, which
will print out an error, and then run the `riscv authdata_read` and
`riscv authdata_write` commands. When authdata_write() notices that the
authenticated bit went high, it will call examine() again.
Example usage (very simple challenge-response protocol):
```
init
set challenge [ocd_riscv authdata_read]
riscv authdata_write [expr $challenge + 1]
reset halt
```
Change-Id: Id9ead00a7eca111e5ec879c4af4586c30af51f4d
2018-02-27 09:27:00 -08:00
9033d99491
Merge pull request #217 from riscv/disable_target64
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build with --disable-target64
2018-02-26 12:06:47 -08:00
3c1c6e059c
Merge pull request #203 from riscv/sysbusbits
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Add support for system bus master, and for targets that don't have any program buffer
2018-02-20 09:22:22 -08:00
d570f89303
target/riscv: add some switch fallthrough comments
2018-02-20 14:31:31 +01:00
6b02ab4196
Fix build with --disable-target64
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Change-Id: I5acf47845ff197a1aeb31356de7e4cd8ce63d476
2018-02-19 15:07:10 -08:00
352e6b82ed
Merge pull request #208 from riscv/run_from_trigger
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Handle resuming from a trigger...
2018-02-19 13:42:50 -08:00
1b37f60969
riscv-compliance: Check that DPC is sign extended properly.
2018-02-13 15:02:31 -08:00
8f7195af76
riscv-compliance: Turn off ABSTRACTAUTO until the appropriate time
2018-02-13 13:47:14 -08:00
313885cb3b
riscv-compliance: whitespace fixes
2018-02-13 13:08:15 -08:00
2e525e391f
riscv-compliance: get it compiling against riscv branch again
2018-02-13 13:01:56 -08:00
88370b3989
riscv-compliance: fix some macros which were renamed
2018-02-13 11:44:53 -08:00
f3bce93dc8
Merge remote-tracking branch 'origin/riscv' into HEAD
2018-02-13 10:57:32 -08:00
5c543ee3a1
complete reset before writing to hartsel field
2018-02-07 16:06:02 -08:00
ace6b7e49a
Handle resuming from a trigger...
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... by disabling all triggers, single stepping, enabling them, and then
resuming as usual. Without this change, you'd just be stuck on an
address trigger and would have to manually disable it.
Change-Id: I5834984671baa6b64f72e533c4aa94555c64617e
2018-02-07 13:30:23 -08:00
5cf705d360
Merge remote-tracking branch 'origin/riscv' into HEAD
2018-02-06 10:26:22 -08:00
a80ab87efd
Add unreachable return for mingw build.
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Change-Id: I8c0c4d7be8f6f28638cc2b5ae8114f5c8f95f94b
2018-01-31 16:55:43 -08:00
7114ef485c
Fix cut and paste bug.
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Change-Id: I1c554cbe3d7cb7845bc62f14ae6b8dff107eb192
2018-01-31 16:45:33 -08:00
bb2c25c5ce
Make OpenOCD work when there is no program buffer.
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Fixed abstract register access for registers that aren't XLEN wide.
Avoided excessive errors cases where we attempted to execute a fence but
failed.
Don't mark all the CSRs as caller-save. gdb was saving/restoring
dscratch, which broke function calls as a side effect. dscratch is
accessible for people who really know what they're doing, but gdb should
never quietly access it. The same is probably true for other CSRs.
Change-Id: I7bcdbbcb7e3c22ad92cbc205bf537c1fe548b160
2018-01-31 15:33:45 -08:00
6f0d70f5c8
Mention register name instead of number in error
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Change-Id: I5be5e57418e672fc76383fc24635cdbfb1e65578
2018-01-30 12:30:39 -08:00
ee93a9b2f1
Add error handling code to system bus read/write
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It's not tested because spike never reports any busy errors since every
access happens instantaneously.
Change-Id: If43ea233a99f98cd419701dc98f0f4a62aa866eb
2018-01-30 08:53:46 -08:00
0f0c5b1ff5
Merge branch 'riscv' into sysbusbits
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Change-Id: Ib7921c73a4bdd586703031be3509d1dec9bb3913
2018-01-29 11:39:14 -08:00
6a98fb7076
Detect hartsellen, limiting which harts we probe
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Tested with doctored spike with hartsellens of 0, 1, 3, and 10.
Change-Id: I97f57c7d03b076792d5ecd66545d9b9e853ed515
2018-01-26 16:39:58 -08:00
5184c32125
Clear errors that we see.
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Also WIP towards handling busy errors, but I'm putting that on hold
while I change the spec...
Change-Id: Iccf47048da46e75b0d769e56004fd783bba1dbf0
2018-01-26 15:43:05 -08:00
b67379700b
Add support for v1 system bus access.
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This is functional, but doesn't handle errors.
Change-Id: Ifb46af1b0b567f3c2a6135b2ad5eb7ba63a3f595
2018-01-26 15:43:05 -08:00
beac00149c
Use new debug_defines.h
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Change-Id: Iefc8424343dbed05fa9dacc626829955fc16f299
2018-01-26 15:41:45 -08:00
2d263bae84
Make all memory logging lines consistent.
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Also reduce a few 64-bit variables to 32 bits, which is all they need.
Change-Id: I23e431b7eed4a63803add93a1bb328a3631631d6
2018-01-24 13:53:11 -08:00
42e601afc1
Merge pull request #191 from riscv/scanbuild
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Fix some niggles found by clang's static analysis.
2018-01-24 07:59:47 -08:00
553a63808c
Fix some niggles found by clang's static analysis.
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Change-Id: Id476227e1bd02e067f0cc4da9bc7ffb3d9d30535
2018-01-23 15:16:23 -08:00
3839cbf0ad
Add some error checking to examine().
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Fixes #183 .
Change-Id: I6fb45adf4c97ea339c9d4ca3b372a09b18e3b56e
2018-01-19 13:58:02 -08:00
7f368468c8
Remove dead code.
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Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
2018-01-15 12:07:20 -08:00
6f9585068f
Merge pull request #172 from riscv/dbus_read_comment
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Add a comment in dbus_read
2018-01-10 15:30:56 -08:00
0d60a29c21
Merge pull request #178 from riscv/cleanup
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Rename dummy variable to be correct.
2018-01-10 15:16:40 -08:00
29c7a76708
Muck with mstatus to always be able to read FPRs
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Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
2018-01-09 12:06:11 -08:00
fd506fa839
Propagate register read errors.
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Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
2018-01-08 11:53:02 -08:00
0e3869cbf6
Merge pull request #179 from riscv/multicore_hart_selection
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Select current hart before reading memory.
2018-01-05 14:07:38 -08:00
11e51af3b1
Merge pull request #173 from riscv/warn_names
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Use register names instead of numbers in warnings
2018-01-05 13:07:08 -08:00
37434ffd77
Rename dummy variable to be correct.
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Change-Id: I329404894227bb3cf563382e1adf0edda702543b
2018-01-05 13:05:33 -08:00
6f3913cedc
Select current hart before reading memory.
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This avoids trying to read memory from the wrong hart, if the current
hart was changed by an earlier call (eg. to poll()).
Change-Id: I73da1e01c8d01d68f01ac7fdd6c548380a70cfd3
2018-01-04 17:12:01 -08:00
097d62d159
Make delay update messages debug instead of info.
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They confuse users otherwise.
Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
2018-01-04 13:36:53 -08:00
33aad3524b
Add a comment in dbus_read
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This just comments the current behavior
2018-01-04 13:27:35 -08:00
07e19e17cb
Use register names instead of numbers in warnings
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Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
2018-01-04 13:27:18 -08:00
365c79c3ff
Get rid of abort() calls.
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Also changed a few asserts that could trigger due to broken hardware.
Fixes Issue #142 .
Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
2017-12-27 13:45:50 -08:00
06445f5743
Propagate error instead of calling abort().
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As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.
Partly addresses Issue #142
Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
2017-12-26 15:04:02 -08:00
4fa3d819d2
Remove unused code.
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Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
2017-12-26 14:27:44 -08:00
d942bce996
Conform to OpenOCD style guide.
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Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
2017-12-26 11:38:11 -08:00
1f66c7827b
Fix flash/run algorithm with new register names
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Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
2017-12-21 16:41:50 -08:00
33ef457c6a
Merge pull request #155 from riscv/debug_defines
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Update debug_defines to the one used with spike.
2017-12-21 15:17:43 -08:00
a81ad34af3
Merge pull request #148 from riscv/macbuild
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Use %ll instead of %L in scanf.
2017-12-21 15:16:57 -08:00
5892b26259
Update debug_defines to the one used with spike.
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Change-Id: I627c6ee557d98239227324c33f9b89f6280cbf93
2017-12-21 15:05:12 -08:00
fa385bdcd5
Use parens after if.
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I'm surprised this built with gcc before.
Fixes Issue #150 .
Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
2017-12-21 12:43:22 -08:00
11c261cd50
Add `riscv expose_csrs` command.
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This lets users tell OpenOCD which non-standard CSRs exist on their
target, that will also be accessible and whose existence will be
communicated to gdb.
Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
2017-12-19 10:41:48 -08:00
5f86f7208d
Hide supervisor registers if there is no S mode.
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Also update encoding.h.
Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
2017-12-19 10:41:48 -08:00
f55d1a2030
Give FPRs ABI names.
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Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
2017-12-19 10:41:48 -08:00
c7cddd2b5c
Remove some debug printfs.
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Change-Id: I09989d4c0e102889ecb0eedbd3f4138f8b7bdb8c
2017-12-19 10:41:48 -08:00
56ad0e5b30
Avoid another assertion failure.
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Change-Id: Ia54f778152974164697b712c360918e17a127d95
2017-12-19 10:41:48 -08:00
10c17fdf17
Read misa before using it to check for extensions.
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Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
2017-12-19 10:41:48 -08:00
ec1c814017
Don't rely on hart count until it's correct.
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Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
2017-12-19 10:41:48 -08:00
46715c7d8a
Remove no-longer-true comment.
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Change-Id: I888680e73682582438a0de0496238867f1604754
2017-12-19 10:41:48 -08:00
120477b2a2
Simplify examine()
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Now we don't have to play tricks fooling other parts of our code that
might assert.
Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
2017-12-19 10:41:48 -08:00
37278cf2ec
Make priv register 8 bits.
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(It's really only 2 bits, but something wonky happens between gdb and
OpenOCD if I make it that size.)
Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
2017-12-19 10:41:48 -08:00
f341db9f72
WIP xml register for 0.11.
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On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.
Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
2017-12-19 10:41:48 -08:00
8926e66d3a
Hide unknown registers, which probably don't exist
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Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
2017-12-19 10:41:48 -08:00
26a54452d2
Fix register names.
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Use the ABI ones for every register that we have one for.
Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-12-19 10:41:48 -08:00
7c989698a1
WIP better CSR names, and include only existing
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Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
2017-12-19 10:41:48 -08:00
a5cb0b2270
WIP. Hide FPRs if the hart doesn't support F/D.
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Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
2017-12-19 10:41:48 -08:00
e648856a41
`make all` debug tests now pass.
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Also properly support (I think) D extension on RV32.
Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
2017-12-19 10:41:48 -08:00
c421fefdcb
Checkpoint that seems to work.
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Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
2017-12-19 10:41:48 -08:00
1e43d32e01
Use %ll instead of %L instead of scanf.
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Mac build barfs on L, and the manpage says they're equivalent.
Hopefully fixes #147
Change-Id: I3aa57775731f3f5ceb03097cae2a9dc6fd426dcd
2017-12-15 15:31:36 -08:00
6aff46adcc
Fix cut and paste bug.
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Now reading 64-bit FPRs on 32-bit harts using scratch memory might work.
Change-Id: Ie8c0fc689386c6e724ecab5e8c855e725fa8dd97
2017-12-14 13:51:13 -08:00
0a65a6527d
Fix build.
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Change-Id: I4e3a36fac77fefa271ae9facbaa990fa330501ae
2017-12-11 12:58:20 -08:00
e50ee46a6f
Merge pull request #131 from riscv/small_progbuf
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Support program buffers that are just 2 instructions large
2017-12-11 12:52:31 -08:00
4d5f74fbe6
Update encoding.h.
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Change-Id: Id653500aa525746e8824ff5fd2850c62c8c21c08
2017-11-27 13:23:33 -08:00
52cdf286ca
Add missing return.
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Change-Id: Ida32482903cdfd8eeb043088e84bb1f4f5ac673c
2017-11-16 15:58:08 -08:00
9f56a9643d
riscv-compliance: remove some compile warnings
2017-11-02 09:34:43 -07:00
e435011713
Merge commit '8304e1b' into HEAD
2017-11-01 13:44:51 -07:00
e28abf7c9e
Merge branch 'riscv' into small_progbuf
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Change-Id: I1d48cb1f8448ebbf98c8bb369928d1e7a7a78c75
2017-11-01 13:38:17 -07:00
db754536e8
Support 64-bit FPRs on RV32.
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Because there is no instruction that moves just half of a 64-bit FPR
to/from a GPR, we need to use scratch memory for this operation. This
code can theoretically use:
1. DMI_DATA, if it is memory mapped in the target.
2. DMI_PROGBUF, if it is writable in the target.
3. A user-configured address.
I have only tested this code very lightly. One reason is that gdb thinks
that on RV32 harts every register is 32 bits wide. Another is that this
is mostly proof-of-concept to satisfy the small program buffer code
review, which I don't want to drag out forever.
Existing tests don't realize that floating support was broken with
RV32D, and don't realize that it still doesn't work because of the gdb
problem mentioned above.
This change improves Issue #110 but there's more work to be done.
Change-Id: I99b8a36e5fea26f1d9e16e36cf99adc7be26b944
2017-10-27 13:15:22 -07:00
1672f9a60d
Merge remote-tracking branch 'origin/riscv' into riscv-compliance
2017-10-25 15:41:41 -07:00
1acb128290
Remove unused variables.
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Change-Id: I678d0a65c22792895375dc6916381f81af8f83e4
2017-10-25 13:37:56 -07:00
23bd6d08c9
Remove more unused functionality.
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Change-Id: I43283b9556c959f891a587fb39bdd1ab9206e8af
2017-10-24 15:11:33 -07:00
dbecbfee99
Add a fence after memory writes.
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Change-Id: I5137479b685f735aa573cec5d40170016c40f597
2017-10-24 12:15:25 -07:00
59a0340261
Remove more unused code.
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Change-Id: I962660f58d948f85df6e073065e15e5d8f4a02b6
2017-10-24 11:38:39 -07:00
8432b7cf3d
Remove more unused code.
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Change-Id: Id91237c163d86e8f4d039503ca33b4ad7571ecd1
2017-10-24 11:34:48 -07:00
3ba6d46fc2
Remove unused functionality.
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Change-Id: Ic70cebd62bbd04f7ae5566504fbb279a11de57f0
2017-10-23 14:45:58 -07:00
5425c871c9
Properly fix memory read when encountering busy.
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Change-Id: I377054495e860076edc2f38d1cc0f11c23f98d3b
2017-10-23 14:13:46 -07:00
a3a137062d
Pay attention to impebreak.
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This required updating debug_defines.h, which caused a few other small
cleanups as well.
Change-Id: I3c2cb418d7eff3093d7664c5563b2af5e8b530eb
2017-10-18 14:21:23 -07:00
85bfab36ad
Remove unused functionality.
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Change-Id: I0c1464e2e6aa12d0cb1025ed0a7c1c483e7403b7
2017-10-18 12:47:07 -07:00
5d3f5c35d2
Still restore registers if an access failed.
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Change-Id: I11571f0926f69a34f95b4929f633fdecd3a4e810
2017-10-18 12:32:41 -07:00
7edd9b1786
Fix FPR access.
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Change-Id: I1379de87904f1cf40b45d1a5490249e3ba90d7d0
2017-10-18 11:47:15 -07:00
a0623b2fa8
Don't crash when encountering RV64.
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Change-Id: Ie915ce830c3499919e4918ad443a5e225cf8c4d9
2017-10-17 11:58:51 -07:00
65be0776d8
Memory read/write works if the core can keep up.
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Change-Id: Ieca50ece266fbc9d2ff16a5cc2e6b4b926ad5e6f
2017-10-17 11:52:07 -07:00
fbe2980eb7
MemTest64 passes.
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Change-Id: I75996b71c3f31025c89ef596a08e01d191405336
2017-10-17 11:15:51 -07:00
d94b38279a
Memtest{16,32} pass.
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Change-Id: I15c2a4fd2bb9a7b30762d07f3b3a74d2f477746b
2017-10-16 21:08:59 -07:00
7ec7bc32fe
At least some memory writes work.
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Change-Id: I6fcf261341f10ec34df01bb844744439d02471a8
2017-10-13 12:50:02 -07:00
e7bb815e87
Register read/write might be working.
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Change-Id: I6c51d6157dde56d8cd666b4d30ec7bbc7a4bef9f
2017-10-12 14:38:52 -07:00
94e8250713
WIP; doesn't work.
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Change-Id: Ia407e82ccbd2044ad61e0845d285dd5765154476
2017-10-12 11:45:52 -07:00
77802af655
Remove duplicate progbuf size variable.
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Change-Id: I662ff84d13ecfc7faae51406a4df57a3643116f0
2017-10-10 16:27:51 -07:00
24658db50e
Fix compile warnings.
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Partly fixes #124 .
Change-Id: I3a7fd65c643e40b142709806cb9fb4cc62bb955f
2017-10-04 16:02:30 -07:00
abe7eba25a
Merge pull request #118 from riscv/priv
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Fix priv access
2017-10-04 12:52:21 -07:00
a3c26250bf
Merge pull request #116 from riscv/multigdb
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Fix trigger code to work with multi-gdb mode instead of RTOS mode
2017-10-03 11:53:58 -07:00
f9f303923e
target/riscv/asm.h: use tab for indentation
2017-10-03 00:36:22 +03:00
f5a69e547f
target/riscv/program.c: fix clang warning
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- I'm not sure I understand the logic behind the original statement,
but on macOS it fails to compile.
2017-10-03 00:23:14 +03:00
728a617bd4
target/riscv: Silence -Werror=return-type
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- clang compains about the functions not returning a value
2017-10-03 00:17:57 +03:00
e64bb8c44a
Fix priv access on 0.13.
2017-09-30 14:15:37 -07:00
6795270a8e
Make priv readable in 0.11.
2017-09-30 13:31:57 -07:00
1083352576
Share register numbers between 0.11 and 0.13.
2017-09-30 13:13:03 -07:00
51f73a6769
Fix triggers for multi-gdb mode.
2017-09-26 15:40:49 -07:00
744894e965
Better debug messages.
2017-09-26 15:40:41 -07:00
f0195868d3
Fall back on ndmreset if hartreset is unsupported.
2017-09-21 14:53:12 -07:00
fe36097ff8
Fix reset for multicore.
2017-09-21 12:42:40 -07:00
848fe0ffcf
Cleaning up single-hart reset.
2017-09-19 17:41:52 -07:00
4e701669b7
Merge pull request #113 from riscv/macos_build
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Add clang build
2017-09-19 14:11:10 -07:00
60354cbea2
clang fix, don't allow unaligned uint64_t pointers
2017-09-18 14:56:46 -07:00
ed9a04bde9
Remove unnecessary abs().
2017-09-18 14:35:47 -07:00
0abd94b50c
Make constants unsigned for clang.
2017-09-18 14:23:59 -07:00
604dfa0dcc
Try to fix some clang warnings.
2017-09-18 14:03:33 -07:00
157a67a98a
Be more clear in multi-core systems without -rtos
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Don't print out there's a hart with XLEN of 0.
2017-09-18 11:29:14 -07:00
ce20be3d78
Add support for F extension.
2017-09-14 16:23:47 -07:00
f9b2549e20
Tell user how to increase timeout.
2017-09-11 12:11:24 -07:00
a6ec1a0e68
Add timeout to another infinite loop.
2017-09-11 11:35:47 -07:00
12aca4ab7e
Merge branch 'riscv' into keepalive
2017-08-30 12:09:51 -07:00
3c25b9a0c4
Merge pull request #105 from riscv/memread
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memory read is now completely stable even on intermittently slow targets
2017-08-29 17:33:51 -07:00
6721988ce3
Ensure read_memory() only reads each address once.
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Previously it might read an address multiple times if an abstract
command took longer to execute than expected.
The new implementations reads from the target how far it has gotten
along reading memory, and resumes from there if cmderr=busy.
This ended up being a bigger change than I envisioned, but in the end it
deleted more lines than it added, so I'm happy. :-)
2017-08-29 17:25:04 -07:00
2efc415db4
Finally nailed memory read on slow targets
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The downloaded program now post-increments, and there's no longer an
attempt to read the current address from the target. This made it easier
to fix the problem where at the start of the loop the current address
was already read (in regular entry) or has not yet been read (when the
first round through the loop encountered busy more than once, or busy
was encountered at least once later on).
2017-08-28 11:17:55 -07:00
5f53655e65
Fix off-by-one error.
2017-08-26 18:25:10 -07:00
eef9442aa7
Remove redundant code.
2017-08-26 17:50:05 -07:00
5bdee8bc66
Fix off-by-3 error on 64-bit targets.
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This caused everything to fall apart when debugging slow 64-bit targets.
2017-08-26 17:49:13 -07:00
8bcec87cc1
Remove unnecessary \n
2017-08-26 16:53:00 -07:00
92ef328161
Don't reset DMI when an abstract command is busy.
2017-08-25 18:14:08 -07:00
a9bcc48064
Remove unnecessary newlines.
2017-08-25 18:14:08 -07:00
322669ca98
Merge pull request #95 from riscv/memread
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Fix block memory reads on slow targets.
2017-08-25 16:57:07 -07:00
4d0e88d887
Merge pull request #100 from riscv/riscv_timeout_commands
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riscv: Add commands for setting timeouts
2017-08-25 09:49:15 -07:00
6e16ef2bd4
Merge remote-tracking branch 'origin/riscv' into riscv-compliance
2017-08-15 17:22:48 -07:00
6200d9a180
Merge branch 'riscv_timeout_commands' into riscv-compliance
2017-08-15 17:22:08 -07:00
94de39c221
riscv: Put commandd_handlers before they are needed. Tabs vs spaces.
2017-08-15 17:04:59 -07:00
879c274cb9
riscv: Add commands for setting timeouts
2017-08-15 15:59:40 -07:00
3ec1772c96
riscv: Add commands for setting timeouts
2017-08-15 15:55:09 -07:00
0ff4103a26
Reset address if target was busy during bust write
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Improve Issue #98 .
DebugCompareSections is still failing for me (with an instrumented
sometimes-slow spike), but MemTestBlock now passes reliably.
2017-08-15 15:47:35 -07:00
5c39079a62
Remove some unnecessary casts.
2017-08-15 14:29:24 -07:00
5092f96105
Add some keep_alive()s for use with slow targets.
2017-08-15 13:31:06 -07:00
0d74c8689d
Fix block memory reads on slow targets.
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The interesting new code concerns ignore_prev_addr and
this_is_last_read.
Additionally, I tweaked some debug output, and optimized
riscv_batch_run() when the batch is empty.
2017-08-14 15:02:19 -07:00
25eedb94a5
Merge remote-tracking branch 'origin/riscv' into riscv-compliance
2017-08-14 12:08:58 -07:00
2706df0ec3
Fix a corner case in block memory read.
2017-08-13 14:14:23 -07:00
3109da7dfd
Force actual read from prog buffer for the last transaction in read_memory()
2017-08-12 14:51:12 -07:00
e676d3dae6
Fixed off-by-one error in previous commit
2017-08-11 17:46:35 -07:00
39b01259fa
fixed memory leak introduced by previous commit
2017-08-10 16:37:50 -07:00
b5692585de
Fix reads beyond requested memory range
2017-08-10 14:27:11 -07:00
efcfcf555f
Fix assertion failure when reading from address 0.
2017-08-09 12:42:17 -07:00
46b5f913c7
Display register numbers in a more usable format.
2017-07-27 13:45:26 -07:00
b032eb1bcc
Use a wall clock timeout to complete reset.
2017-07-16 11:48:12 -07:00
f0f1df1061
Fix infinite loop in reset.
2017-07-14 12:50:11 -07:00
c8015e8dc1
riscv compliance: More post-test cleanup
2017-07-13 08:00:22 -07:00
d60dbd60e8
Share trigger code between 0.11 and 0.13 code.
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The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.
In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.
2017-07-12 19:54:40 -07:00
20d46b8bf0
Merge remote-tracking branch 'origin/riscv' into riscv-compliance
2017-07-12 18:46:26 -07:00
66fa38add7
riscv-compliance: Halt harts again at the end of the test.
2017-07-12 18:44:41 -07:00
2deb02695e
Forgot to commit this follow up to PR #79
2017-07-12 17:51:38 -07:00
09bf86e31a
Keep around cmderr for callers to inspect.
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Use this to only change abstract register access behavior when cmderr
explicitly says the requested operation is unsupported.
2017-07-12 14:36:09 -07:00
856f70fe44
Try abstract register writes as well.
2017-07-12 14:13:31 -07:00
f37e93bbc0
Try using abstract commands to read registers
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This is the only way the spec guarantees that GPRs are accessible, and
depending on the implementation this might be the only way that CSRs are
accessible.
Also changed the debug code that parses out DMI fields to be simpler to
maintain (albeit a little slower).
riscv013_execute_debug_buffer() now automatically clears cmderr if the
command fails. That feels like the right behavior. (It does return the
error to its caller.)
2017-07-12 14:13:31 -07:00
da74f511b9
Merge pull request #80 from riscv/triggers
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Disable debugger-set triggers on connect
2017-07-11 12:13:56 -07:00
10a61000b5
Use LL for 64-bit defines, as Windows is LLP64
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This should also fix bugs on ILP32 systems.
2017-07-10 13:45:42 -07:00
4072fa493b
Disable debugger-set triggers on connect
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When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.
To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.
Hopefully this sets us up to in the future share the code to set/remove
triggers as well.
2017-07-10 10:26:24 -07:00
31e5b53a46
Merge pull request #74 from riscv/build32
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Fix 32-bit build errors.
2017-07-06 13:41:47 -07:00
6842fd2c10
riscv: Add more TODO compliance comments
2017-07-05 17:59:30 -07:00
bdc38561c0
riscv: Clean up reset/dmactive/step compliance test
2017-07-05 17:54:55 -07:00
2b94888100
riscv: Add single-step, reset, and dmactive to the compliance test.
2017-07-05 15:11:40 -07:00
87abbe4a51
Merge remote-tracking branch 'origin/riscv' into riscv-compliance
2017-07-05 11:02:30 -07:00
321619946b
Merge pull request #73 from riscv/old_triggers
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Add back support for type 1 triggers
2017-07-03 13:52:16 -07:00
3cff4213a4
Merge pull request #69 from riscv/multi-gdb
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Fix the multi-GDB mode bugs
2017-07-03 13:18:06 -07:00
450307b66f
Fix 32-bit build errors.
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I only compiled the source. Didn't have the tooling installed to link.
Hopefully that's good enough.
Fixes #71 .
2017-07-03 12:17:07 -07:00
f18fd83ac7
Fix trigger set/clear bug.
2017-07-03 11:52:35 -07:00
6c627e9ea9
Add back support for type 1 triggers.
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They were implemented, and people want to keep using them.
Also make OpenOCD tolerate cores that have $misa at 0xf10 instead of the
current address of 0x301.
Actually return an error when we fail to read a CSR.
Tweak cache_set32() debug output.
2017-07-03 11:01:10 -07:00
99a3673507
Fix comment about saving the temporary register in examine procedure.
2017-07-01 15:09:23 +03:00
7d451e00f5
Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction.
2017-06-30 19:15:58 +03:00
7bc23c7776
riscv: Add some comments on what else compliance test needs
2017-06-28 19:36:22 -07:00
434fb3708a
riscv: Correct DPC masking in compliance test.
2017-06-28 19:36:22 -07:00
e32a8c911d
riscv: Fix AUTOEXEC test for 32-bit cores
2017-06-28 19:36:22 -07:00
4101740928
riscv: add compliance tests for DPC and DCSR
2017-06-28 19:36:22 -07:00
e17ca3a31d
riscv: More compliance tests for core registers.
2017-06-28 19:36:22 -07:00
222850df55
debug: add a 'wfi' to compliance test.
2017-06-28 19:36:22 -07:00
9e76ec1779
riscv: Compliance test for HALTREQ/RESUMEREQ R/W
2017-06-28 19:36:22 -07:00
ccc605158a
riscv: Added several compliance test items
2017-06-28 19:32:38 -07:00
95ee7975ea
riscv: Add skeleton of RISC-V v013 compliance
2017-06-28 19:32:38 -07:00
7a4948c126
riscv: initial checkin of a 'compliance test' command.
2017-06-28 19:32:38 -07:00
b6f8efbf44
Check for errors in read_csr().
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Also slightly improve debugging output.
2017-06-27 15:11:06 -07:00
d77c4a953c
Don't set breakpoints on disabled harts
2017-06-21 12:25:20 -07:00
689d0fcaf6
No longer hard-code the non-RTOS hart to 0
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I was just being lazy here.
2017-06-21 12:25:19 -07:00
4bdb042224
Allow memory writes to proceed on all harts
2017-06-21 12:25:19 -07:00
a277416a39
Refactor examine, to avoid some assertions
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Now that we're supporting non-RTOS multi-hart mode there's some more
assertions that you're running on the right hart. Those assertions
aren't sane very early in examine, so I avoid them.
2017-06-21 12:25:19 -07:00
788908fcf0
Factor out checking if harts should be used
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Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled". This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.
2017-06-21 10:09:16 -07:00
9f4cac5a38
Set current_hartid from coreid
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This avoids a bunch of RTOS special cases.
2017-06-20 17:19:05 -07:00
9cd98058a0
Set hardware triggers on all harts.
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Right now we're using "threads" to represent harts. gdb/OpenOCD assume
there's only one set of hardware breakpoints among all threads. Make it
so.
2017-06-20 13:10:35 -07:00
10518351bb
Don't immediately segfault with -rtos on v0.11.
2017-06-20 11:32:42 -07:00
ccdd26e3ef
Comment curious code.
2017-06-20 11:32:42 -07:00
927f9d8873
Update list of "threads" when harts are discovered.
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This ensures that "info threads" is accurate as soon as gdb connects.
Also print out number of triggers that is discovered in examine().
2017-06-20 11:32:42 -07:00
4d264b3579
Put early DEBUG notice of XLEN back.
2017-06-19 08:46:02 -07:00
6082f35a55
Update debug_defines. Clarify debug output.
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Update debug_defines from the spec, commit 920ec9a690.
Decode dmstatus scans in the debug output.
2017-06-16 14:02:25 -07:00
fd81f7fcac
Fix comment.
2017-06-16 14:02:25 -07:00
851849a295
Tell the user about detected harts.
2017-06-16 14:02:25 -07:00
3abb347bd9
Tighten up debug output.
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Assuming the program allocating code works, we don't need its output.
Only output parts of the debug RAM that are actually doing something.
2017-06-16 14:02:25 -07:00
ac2da40f74
Fix indentation to match OpenOCD style.
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This change is just in the whitespace. There are no code changes.
See http://openocd.org/doc-release/doxygen/stylec.html
2017-06-15 12:44:50 -07:00
363a0a2bf2
Merge pull request #64 from riscv/release-fixes
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Two fixes from the release branch
2017-06-15 12:43:46 -07:00
50a223ef9a
Fix print statements to work with 64-bit addresses
2017-06-15 12:24:37 -07:00
afc9eb6c47
Jump to the RTOS hartid after halting
...
When I disappeared the polls everywhere I forgot to sanitize the hartid
after halting. This is an invariant that GDB expects: when you return
from a halt whatever thread is marked as currently selected is the
thread that the next register accesses reference.
2017-06-15 12:16:33 -07:00
099a3020d2
Clear abstract errors from register_read_direct
2017-06-15 12:16:24 -07:00
64af052911
Fix the build.
...
Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.
Smoketest indicates everything is working more or less as before.
2017-06-13 12:33:01 -07:00
6be600318c
Fix dmi_read() indentation; remove \n in LOG_ERROR
2017-06-08 12:31:08 -07:00
c3b344d1c0
riscv: Move the initialization of the field inside the structure for consistency
2017-06-07 21:06:33 -07:00
459b39ec67
riscv: v13 -- dmi_write must still check for the OP result
2017-06-07 21:06:33 -07:00
11008baee3
%p already includes 0x (on gcc)
2017-06-06 11:51:15 -07:00
ab77c5d792
Invalidate the register cache when rtos_hartid==-1
...
This means I don't know what hart to look at, so I might as well
invalidate the register cache. Without this, you might get stale
registers the first time you ask for them.
2017-05-25 13:14:31 -07:00
faa6123e36
Invalidate the register cache on step, resume, reset
...
I thought OpenOCD did this, but it looks like that doesn't happen when
runningi in RTOS mode. With this I can get to the end of most of the
RTOS tests, but they SIGINT instead of exiting.
2017-05-25 13:14:31 -07:00
e12f5575ef
riscv-v11: Don't perform unexpected operation in cache_write
2017-05-22 22:02:01 -07:00
c431c0eb25
Check for abstractcs.busy, not just CMDERR_BUSY
...
This fixes a race condition when reading/writing memory.
2017-05-15 17:40:28 -07:00
a8cf04b839
Go back to 32-word read/write buffers
...
The larger buffers are really slow on Spike.
2017-05-15 16:57:25 -07:00
e31761df64
Don't re-read registers after they're written
...
This was just a sanity check.
2017-05-15 16:57:08 -07:00
9d308db2bc
Print out the actual CSR that's read
2017-05-15 16:56:50 -07:00
8252b9d36c
Build fixes
2017-05-15 13:39:58 -07:00
af6e04d5c0
riscv: Remove some compile warnings
2017-05-15 13:36:05 -07:00
bcf2a16b0d
Shim back in some old interfaces for now
2017-05-11 10:41:13 -07:00
563f6acc3c
Allow all harts to be reset
2017-05-09 13:33:20 -07:00
fa8d7adf33
Avoid accessing null target->reg_cache
...
GDB might request registers even if target was not successfully initialized.
2017-05-05 11:05:28 -07:00
95a2eb157a
riscv-013: more consistent parens
2017-05-01 09:42:11 -07:00
458bb20699
riscv-013: Correct sign extension of address on read_memory for lower bits as well
2017-05-01 09:39:59 -07:00
8462750357
riscv-013: Correct sign extension of address on read_memory
2017-05-01 09:37:48 -07:00
ad1cf13ef4
Correct debugging print in read_memory
2017-05-01 08:35:10 -07:00
16de5044d4
Fix an assertion when reading from 0
2017-05-01 08:33:01 -07:00
ba3a56937b
Correct previous hart caching logic
2017-05-01 08:32:43 -07:00
1ec607c726
Clean up unused read_memory code
2017-04-27 12:56:01 -07:00
17d04aded3
Keep calling the old poll on v0.11 targets
...
This is another thing that should be fixed correctly. Essentially this
just uses the old codepath, which works for v0.11.
2017-04-26 15:16:39 -07:00
9d4df3420c
Initialize all registers in examine
...
I'm not sure why this is necessary, but for some reason GDB is asking
for registers before OpenOCD thinks there's been a halt. This is really
just a workaround, but I need to refactor the v0.11 stuff anyway so I
don't want to figure it out.
2017-04-26 15:09:24 -07:00
da66be0161
riscv: Fix some blocking compile warnings
2017-04-26 10:23:53 -07:00
8dea2908b7
Add 64-bit and multihart support
...
This is a major rewrite of the RISC-V v0.13 OpenOCD port. This
shouldn't have any meaningful effect on the v0.11 support, but it does
add generic versions of many functions that will allow me to later
refactor the v0.11 support so it's easier to maintain both ports. This
started as an emergency feature branch and went on for a long time, so
it's all been squashed down into one commit so there isn't a big set of
broken commits lying around. The changes are:
* You can pass "-rtos riscv" to the target in OpenOCD's configuration
file, which enables multi-hart mode. This uses OpenOCD's RTOS
support to control all the harts from the debug module using commands
like "info threads" in GDB. This support is still expermental.
* There is support for RV64I, but due to OpenOCD limitations we only
support 32-bit physical addresses. I hope to remedy this by rebasing
onto the latest OpenOCD release, which I've heard should fix this.
* This matches the latest draft version of the RISC-V debug spec, as of
April 26th. This version fixes a number of spec bugs and should be
close to the final debug spec.
2017-04-26 09:10:49 -07:00
3dc066382b
Properly consider 'reset halt' and do halt or resume as needed
2017-04-10 12:03:15 -07:00
b04c6cb3ed
riscv: Implement the assert/deassert reset functions for v13
2017-04-10 12:03:15 -07:00
14e26040b8
riscv: move value read to after autoexec is cleared.
2017-04-04 16:33:17 -07:00
9c1f6ea28b
riscv: Correct the autoexec in read_mem
2017-04-04 16:22:55 -07:00
eb90a5e05e
riscv: Use write-1-to-clear for CMDERR, not write 0 to clear.
2017-03-30 14:27:28 -07:00
03fa9d22c4
Don't set abstractauto at the start
2017-03-23 14:50:40 -07:00
c61b3efe9a
riscv: Retry failed memory reads
2017-03-22 17:51:46 -07:00
98420e377a
riscv: add missing variable declaration.
2017-03-21 23:47:21 -07:00
09da0c812f
Clear autoexec correctly
2017-03-21 17:20:11 -07:00
6033850415
Wrong autoexec
2017-03-21 17:20:11 -07:00
0c790d385d
Builds
2017-03-21 17:20:11 -07:00
a70e628620
riscv-v13: wait for idle in read_memory
...
read_memory was doing autoexec-initialized commands, but wasn't using
ac_busy_delay to add delay or wait between the commands. This isn't the optimal
solution, but the whole read_memory sequence needs to be made more efficient
anyway, so this was the quick and dirty solution.
2017-03-15 17:23:21 -07:00
bb39d3b17e
Remove more cruft.
...
Change-Id: I24d545cc259927301851fad446f812e95fd1c557
2017-02-27 20:27:07 -08:00
7f13e90505
riscv: Ensure that hart is halted before attempting to examine it.
2017-02-27 18:53:50 -08:00
b4d38d0997
Remove cruft.
...
Change-Id: I3a370aa3a478ab84c9b2afff7b3f581bd7dc5e06
2017-02-25 10:40:56 -08:00
6f1a498ab9
Use DCSR constants from the debug spec.
...
Replace the constants with the ones from the ISA spec, since those are
not updated as often.
Also delete a bunch of old code.
Change-Id: I9201b1455d64a9d2d203bb362fefaa68cbf35aeb
2017-02-25 10:34:46 -08:00
8f6ddc92e8
Update bits to latest spec.
...
Change-Id: Ib09e1da81c6c0e7c9c6b69e9fe31eda20e3cd6e0
2017-02-25 10:17:27 -08:00
3bd661b679
Speed things up by ignoring return values.
...
The remote bitbang implementation is really slow when reading back data.
During many operations, like writing a block of memory, we don't need to
see the return data. By communicating this to the lower layers, we get
huge speedups. Downloads to spike now are 295KB/s.
That means the gdbserver.py download test now runs to completion,
unfortunately it fails. Everything else is still passing, though, so I'm
committing this change.
Change-Id: I44cc9db1ade0908c1a12d09b23fc8e529a802d88
2017-02-22 16:04:36 -08:00
f9168b09d0
Optimize memory write code, used in download.
...
To spike now we download at 5KB/s. But in real hardware performance
should be pretty OK now.
Change-Id: Ie6086cf156c9a00ac55400870346e27b28e3c755
2017-02-21 20:31:50 -08:00
4e8cf4aeb5
Better error checking in memory access.
...
Change-Id: I985afa433a09f833137f2e244b7eaad2630f6b1a
2017-02-20 17:53:18 -08:00
aba0c0973d
Properly restore s0 and s1 on resume.
...
Now 33/39 of the gdbserver tests pass!
Change-Id: I0cb38fbbcdc2c037ff0ec77229e79f24fa021663
2017-02-20 15:47:31 -08:00
3173314f28
Fix access FPU registers again.
...
Not a great fix. There's still a problem with accessing 64-bit floating
point registers on 32-bit cores.
24 of the gdbserver.py tests pass now.
Change-Id: I69a88ef5fd5581e2c7bf1d78057fd474ae86ff93
2017-02-17 19:03:32 -08:00
071f9a2916
Fix use of REG vs CSR constants.
...
23 gdbserver.py tests pass now.
Change-Id: I32805d615ae5f536f179baf906e0e74a56e80c0b
2017-02-17 12:35:43 -08:00
b363d1a37e
Bunch of register access refactoring.
...
Got rid of the last reference to the old debug RAM code! (Mostly?)
SimpleF18Test passes now.
Change-Id: Iab51d436a50bec9a5e504df7fb3cd6be874da0be
2017-02-17 11:53:37 -08:00
88f14f4d5e
Check busy before triggering another command.
...
This version was able to download code, and run to a breakpoint.
Change-Id: I0ead8350579263d8e55f8df35e2b7af6c374ef21
2017-02-16 14:21:17 -08:00
ef3875a320
Check for errors after read/write.
...
The code doesn't do anything intelligent if errors are found.
But MemTestBlock now also passes. I'm not quite sure why.
Change-Id: I8512f0a96db9e34d3db6a4a9bcef6e56f191d4c1
2017-02-15 20:41:39 -08:00
035b4dd17a
Fix double read, which might have side effects.
...
Now passing MemTest{8,16,32,64}
Change-Id: I286d1e2a388d41853e5aa9049490ddb6135b61f1
2017-02-15 19:05:51 -08:00
713c001242
Make MemTest32 pass.
...
Change-Id: I9be90b07be695c976380f9fd50b971f8bb94f513
2017-02-15 17:10:53 -08:00
79e840aaa7
Some memory access works.
...
MemTest16 passes, but MemTest32 fails.
Change-Id: I17fbc38b4228b27c7fb3dadb15e9c1a2f67bcd65
2017-02-15 15:44:36 -08:00
ceb8dc048d
Make general CSR reads work.
...
Change-Id: Ic9b7e065b7303b3707c28c9b7c496cc1c1e91acd
2017-02-14 12:55:03 -08:00
ae4fda2719
Make it all the way through examine().
...
This includes reading GPRs (although I haven't confirmed the values) and
doing some CSR reading/writing to disable triggers that may be left over
from a previous setting.
Change-Id: I2c627bd002d601e302a40f838087541897c025fd
2017-02-14 11:43:58 -08:00
00925574d5
More dbus->dmi.
...
Change-Id: Ia691f1e7ce909da4d9c16e6d691c4f2cf768a7fb
2017-02-14 09:38:09 -08:00
24033b53d8
Read misa during examine(), using program buffer.
...
Change-Id: Icad5324d216b61207cb5f6024b2deab065658640
2017-02-13 21:29:02 -08:00
0fa8162a8c
dbus -> dmi
...
Change-Id: I4c3343f8f5ffd45e3d76a2218aaa5dee8e546839
2017-02-13 11:13:14 -08:00
e2a5e02d1c
Discover XLEN using abstract reg reads.
...
Change-Id: Ib7480b8e4925cf08e5b59d263bcdcc672a89dc4b
2017-02-13 09:54:05 -08:00
e6221e75c9
Attempt to discover XLEN with abstract reg reads
...
Change-Id: I7ce9c8c0c34bd875dba11596e6f6268320b2fb3a
2017-02-10 19:08:44 -08:00
5e3d9803ab
Halt target in riscv_examine().
...
Change-Id: I11ab915901f2e75f9b728d6cf72c6498e3950ded
2017-02-10 11:31:14 -08:00
075c0e80d1
Add debug_defines.h.
...
Change-Id: I94753f9bed11cbc978daa0f3ea3ecf2023b93893
2017-02-09 09:57:54 -08:00
2ad366e658
Detect and smoketest data and ibuf registers.
...
Change-Id: I7ee4817ec63041a1577b83392d40b676fb67c207
2017-02-08 20:40:37 -08:00
8cac7d0cee
Correctly parse dmcontrol.
...
Change-Id: Ibae425f4ccbe9e504c41e185f264f667e091fca4
2017-02-08 19:47:34 -08:00
8af4a9a053
Update DMI bus width for 0.13.
...
Change-Id: Ieff13a7a0084fe822b7cc6d927727eba4f158ef0
2017-02-07 11:28:50 -08:00
ecc5b6ecad
Add missing header file.
...
Change-Id: I19df5112c2503ec6652f2d09e7324180af5024df
2017-02-05 21:32:44 -08:00
6f78eb1ec1
Add the first difference for 0.13 targets.
...
Just to confirm the 0.13 code takes a different path.
Change-Id: I7f1c9c8f3b586aee001dbeef2213f5f2e6a94f36
2017-02-05 18:21:34 -08:00
8d195afd2d
Use the csrNNN name instead of "mstatus".
...
Fixes flashing code.
Change-Id: Id12c926f5ada009e06f6601362deefec946afc98
2017-02-05 18:19:00 -08:00
d055f86552
Most gdbserver tests pass now.
...
Change-Id: I14a8360d9cf2800ca5e6a44f7e58102b2baef719
2017-02-05 18:09:19 -08:00
5d82a395f1
riscv: disable interrupts for all priviledge levels
2017-01-25 21:51:02 -08:00
d5892f0ee5
riscv: Use proper UINT packing and unpacking routines for disabling interrupts before running algorithms.
2017-01-25 15:23:10 -08:00
5766efe0c3
riscv: Globally disable interrupts when running algorithms.
2017-01-25 11:35:57 -08:00
4a0d3fb035
riscv: implement skeletons for Memory Blank Check and CRC. Otherwise you just get a segfault when attempting to perform these actions.
2016-12-07 15:09:35 -08:00
c1da323144
Fix issue #6 : build failure on gcc 6
...
Change-Id: If890a6d62fdd55befb9057f83726f60721ac8078
2016-12-01 19:15:55 -08:00
7dd48acdc0
Cope better if the target unexpectedly resets.
...
Change-Id: I713f7f8a3afbbb02be0e2f19f4d32778366d37f9
2016-11-25 09:46:55 -08:00
8ee0647365
Flash at 8KB/s, using 10,000 byte working area.
...
If the working area is large enough, every fespi_write() results in just
a single algorithm execution.
Change-Id: I87a12e29f50ef6ea1f46fbd1edf440f9e54a2162
2016-11-18 10:58:26 -08:00
18eedf996c
Use algorithm to speed up fespi flash programming.
...
It's still really slow, at 854b/s, but it seems to work and it's a lot
of new code.
Change-Id: I9dd057bbcc81a56eb558b4f33ac35f6f03c23588
2016-11-16 17:54:55 -08:00
e51b0360f5
Make fpu regs work even if mstatus.fs is 0.
...
Change-Id: I2c283f2de226518ab9a4e0476edada51825b2993
2016-11-01 12:58:37 -07:00
e7a745ed3b
Fix bug with slow targets.
...
Halting didn't work right in slow targets, because some code assumed the
register cache is valid before it was guaranteed to be.
Also made dbus_busy_delay and interrupt_high_delay grow faster, so that
on slow targets it takes less time to learn the correct values.
Change-Id: I948a49d4e3cd0638f5449ab94994406319fd5f42
2016-10-27 13:00:26 -07:00
e6e2070692
Add some comments.
...
Change-Id: Icd7d5eb370c6c893ec4717c92249f35fb100370a
2016-10-24 14:21:34 -07:00
3eb6cf0fc0
Make CLI step and resume work.
...
Change-Id: I027d7032800f909e8d149ed84c11b6e75b75491f
2016-10-20 14:49:23 -07:00
9b0be80d1e
Use reg_cache structure, to make reg command work.
...
Change-Id: I9f1d1f2eab66822c3c47284aa91b52cc34998381
2016-10-20 10:42:28 -07:00
4eba841bfe
Print when we're ready for gdb to connect.
...
This should help gdbserver.py to connect reliably to really slow targets
(ie. simulators).
Change-Id: I8e9adbaf2ebde11b44e15582f036622a2d00c1f9
2016-10-14 12:40:52 -07:00
3f6c2a9f78
Be quiet when the target is just running normally.
...
Change-Id: I7861f16ba6b1b5c1851787ce5d78c02aff0568f6
2016-10-13 10:51:53 -07:00
cb93bb9035
Use an easily changed constant for timeout.
...
Change-Id: I7aace463b0bd9916580e950d60b2940879b27b2a
2016-10-11 16:26:19 -07:00
4882de94cc
Display pc to the user in 'monitor reset init'.
...
Change-Id: Ifb8df31954dfc5a3badef4f0a29eb510a97310a2
2016-10-10 08:22:51 -07:00
a08cef7633
Change invalid access from error to user message.
...
It's not a failure in the debugger or even a real problem if a user asks
to access memory that's not accessible.
Change-Id: I30b8424d5265d1996fe4826012ed160a83f0bc6c
2016-10-03 08:15:04 -07:00
e273e23f41
Fix off-by-one error in assert.
...
Also only do work for debug RAM that actually exists on the target
(exposing the off-by-one error on 32-bit targets).
Change-Id: I37e0005b6a70e949286f1d6494716f3abea03c12
2016-09-29 10:40:50 -07:00
4dbc9962d3
Clear dmode triggers when we first halt the target
...
This helps repeated runs of the testsuite pass, and is probably a good
idea in general.
Change-Id: I89ed167968f8b8817c66f1718f374d0c502780c7
2016-09-29 10:23:46 -07:00
78fe0b56db
Deal with dbus being busy in all cases.
...
Change-Id: Ifede6e05c3c4538f22a52cd0e9833cf3a9983d04
2016-09-29 08:28:31 -07:00
b04d5e8821
Read idle, and test all debug RAM.
...
Read dtmcontrol's idle field to decide how many run-test/idle cycles are
required to communicate with the target.
In riscv_examine(), write and read all of Debug RAM to check the target
is at least somewhat sane.
Change-Id: Ieedb7a50418fa1f5e0d456cde53c52f7fc51662b
2016-09-27 13:06:32 -07:00
c67850b63d
Only write to existing dram. Clear dbus error.
...
Old code would write 64 bytes of DRAM if the dbus was busy in
cache_write().
New code clears the dbus error condition when the bus is busy. (This
part is untested.)
Change-Id: Ia396fe819fa1828bb75726d85513b113cc9e13f0
2016-09-27 08:45:51 -07:00
54c65a9a4b
Improve low-level logging.
...
Now logging is consistent and more readable.
I did remove most logging during riscv_poll() since it clutters up the
log/screen and is not generally helpful.
2016-09-23 14:16:24 -07:00
08228e6f53
Make more code use the scans "class".
...
Helps with consistency, and this is a rare commit that net deletes
lines.
2016-09-23 14:16:24 -07:00
cf1dc0b6cb
Implement hardware triggers that match spec.
...
It's basically working, but the following corner cases are failing:
TriggerDmode
TriggerLoadAddressInstant
TriggerStoreAddressInstant
2016-09-23 14:16:24 -07:00
526bbc5284
Optimize read a bit.
...
Remove some unnecessary scans.
2016-09-23 14:16:24 -07:00
c68b13ed67
Properly mark the cache as clean after its written
...
This reduces the number of scans, but I doubt it noticeably improves
performance.
2016-09-23 14:16:24 -07:00
243233c8b8
Convert some more code for 64-bit.
2016-09-23 14:16:24 -07:00
b04f89076a
Properly write 64-bit PCs.
2016-09-23 14:16:24 -07:00
e3e745abb9
WIP for 64-bit support.
...
GPR register writes/reads seem to work.
2016-09-23 14:16:24 -07:00
2f1b6b5803
Stop using conditional writes.
...
It doesn't help, and makes the spec more complex. Now that I've proven
OpenOCD doesn't need it, I'll remove it from the spec.
2016-09-23 14:16:24 -07:00
5dbad6b0c9
Check for business in block reads.
2016-09-23 14:16:24 -07:00
f8b0f4bf29
Check for exceptions in reads and writes.
2016-09-23 14:16:23 -07:00
f5ae4d864c
Add support for virtual priv register.
...
Users can use this register to inspect and change the privilege level of
the core. It doesn't make any assumptions about the actual underlying
debug mechanism (as opposed to having the user change DCSR directly,
which may not exist in all debug implementations).
2016-09-23 14:16:23 -07:00
5de81da8f4
Remove commented out code.
...
Also added back the initial check that confirms debug RAM is written
correctly.
2016-09-23 14:16:23 -07:00
a916d204b9
Optimize memory read.
...
Saves 8s on the full test suite.
2016-09-23 14:16:23 -07:00
32e7a962c3
Write fence.i before dret.
...
Makes things work if the ROM doesn't contain fence.i (which is slow, so
Andrew took it out).
2016-09-23 14:16:23 -07:00
4ced71b1f1
Log more.
2016-09-23 14:16:23 -07:00
20e2bfe3db
Quickly read all GPRs on halt.
...
gdb will ask for them anyway, and one by one is slow.
StepTest went from 9.7s to 5.3s.
2016-09-23 14:16:23 -07:00
6fac5a41f8
Remove some hwbp debug code.
2016-09-23 14:16:23 -07:00
7dcc0681d4
Speed up some other operations.
2016-09-23 14:16:23 -07:00
1fdcfa7082
Speed up register read.
...
Don't scan an extra sequence just to read the return value.
2016-09-23 14:16:23 -07:00
27b94d36d0
Fix 32-bit build.
2016-09-23 14:16:23 -07:00
668070cc45
Faster download.
...
16K testcase:
Transfer rate: 53 KB/sec, 2222 bytes/write.
2016-09-23 14:16:23 -07:00
9aab0aa068
Minor cleanup.
2016-09-23 14:16:23 -07:00
06f6b5020c
Use optimized cache/program write scheme for most
...
operations.
2016-09-23 14:16:23 -07:00
a1875fbecf
Working on optimized program running.
...
Makes a big difference on the XLEN code (29ms to 8ms). Now to use it in
more places.
2016-09-23 14:16:23 -07:00
9b9653ab7d
Use hardware single step.
2016-09-23 14:16:23 -07:00
eac8933b89
WIP on performance improvement.
...
Also implement empty arch_state to prevent occasional startup crash.
2016-09-23 14:16:23 -07:00
2d02e77bed
Make this compile for 32-bit targets.
2016-09-23 14:16:23 -07:00
aaa8ce10b8
Correctly figure out the number of extant hwbps.
2016-09-23 14:16:23 -07:00
c471cfb63b
Simple execute hardware breakpoint works.
2016-09-23 14:16:23 -07:00
cb57aa55fa
Deal with exceptions on register read.
...
Cache dpc, so we can restore it when it's clobbered by an exception.
2016-09-23 14:16:23 -07:00
b81a846be5
Cache dcsr, since we're reading it anyway.
2016-09-23 14:16:23 -07:00
c8430bb8f4
DebugTest.test_interrupt passes now.
2016-09-23 14:16:23 -07:00
e10d407623
Speed up memory read a little.
2016-09-23 14:16:23 -07:00
4b19b7305f
Save/restore T0 around block writes.
2016-09-23 14:16:23 -07:00
90f458e63f
Reading/writing s1 now works.
2016-09-23 14:16:23 -07:00
0881092d9b
Can successfully run to a swbp.
2016-09-23 14:16:23 -07:00
c364bd0ab5
We can run to a software breakpoint, but
...
gdb doesn't notice we're halted once we hit it, even though riscv_poll()
is setting the target state to halted.
2016-09-23 14:16:23 -07:00
04cfc35147
Use the dram cache to save some scans.
2016-09-23 14:16:23 -07:00
dce4a992a3
Single memory reads/writes work.
2016-09-23 14:16:23 -07:00
1b349df638
WIP hackery.
...
Main thing I added is code to output "verilog" for every JTAG op we do,
so we can run the same thing in simulation.
2016-09-23 14:16:23 -07:00
f40862d87c
Go through run-test/idle once per dbus access.
2016-09-23 14:16:23 -07:00
9f22176618
Reading registers appears to work.
2016-09-23 14:16:23 -07:00
84944ded87
Fix up some register stuff.
...
Now you can attach with gdb, and it'll attempt to read a register. That
will fail because the core won't clear debug interrupt. Adding nops
doesn't help this time.
2016-09-23 14:16:23 -07:00
f634702aaf
Successfully determine xlen.
...
There's a nop in there for no reason, though.
2016-09-23 14:16:23 -07:00
db06dd45a0
Improve error checking.
2016-09-23 14:16:23 -07:00
041e0ccf9e
Selecting dbus is sometimes necessary.
2016-09-23 14:16:22 -07:00
25e8b66b08
WIP registers.
2016-09-23 14:16:22 -07:00
3b60c3aa42
Fix bug when waiting for debugint to clear.
2016-09-23 14:16:22 -07:00
67009979ae
Clearer debug logging.
2016-09-23 14:16:22 -07:00
3b3beb04ef
WIP on registers.
2016-09-23 14:16:22 -07:00
482497c51a
Blind implementation of write_memory.
2016-09-23 14:16:22 -07:00
50ca8ac373
Blind implementation of read_memory.
2016-09-23 14:16:22 -07:00
76fe7db0db
In theory assert_reset/deassert_reset work.
2016-09-23 14:16:22 -07:00
ea6836c5f6
WIP, blind coding.
2016-09-23 14:16:22 -07:00
413ab49dfd
Blind coding new dbus behavior.
2016-09-23 14:16:22 -07:00
feff2dd9e7
Always leave the TAP in Run-Test/Idle.
2016-09-23 14:16:22 -07:00
98f2fa897f
Halt should work now.
2016-09-23 14:16:22 -07:00
Megan Wachs
Ryan Macdonald
Tim Newsome
Kaspar Schleiser
Gleb Gagarin
Liviu Ionescu
Palmer Dabbelt
Dmitry Ryzhov