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riscv-openocd
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Write fence.i before dret. 

Makes things work if the ROM doesn't contain fence.i (which is slow, so
Andrew took it out).
This commit is contained in:
Tim Newsome 2016-06-30 10:41:04 -07:00
parent 4ced71b1f1
commit 32e7a962c3
2 changed files with 8 additions and 7 deletions
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10
src/target/riscv/opcodes.h
View File

@ -116,6 +116,11 @@ static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset)
static uint32_t ebreak(void) { return MATCH_EBREAK; }
static uint32_t ebreak_c(void) { return MATCH_C_EBREAK; }
static uint32_t fence_i(void)
{
return MATCH_FENCE_I;
}
/*
static uint32_t lui(unsigned int dest, uint32_t imm)
{
@ -135,11 +140,6 @@ static uint32_t li(unsigned int dest, uint16_t imm)
return addi(dest, 0, imm);
}
static uint32_t fence_i(void)
{
return MATCH_FENCE_I;
}
static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
{
return (bits(offset, 11, 5) << 25) |

5
src/target/riscv/riscv.c
View File

@ -786,7 +786,8 @@ static int resume(struct target *target, int current, uint32_t address,
dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
dram_write_jump(target, 2, false);
dram_write32(target, 2, fence_i(), false);
dram_write_jump(target, 3, false);
// Write DCSR value, set interrupt and clear haltnot.
uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
@ -1016,10 +1017,10 @@ static int riscv_step(struct target *target, int current, uint32_t address,
int handle_breakpoints)
{
jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
// Hardware single step doesn't exist yet.
#if 1
return resume(target, current, address, handle_breakpoints, 0, true);
#else
// Hardware single step doesn't exist yet.
riscv_info_t *info = (riscv_info_t *) target->arch_info;
uint32_t next_pc = info->dpc + 4;
// TODO: write better next pc prediction code