From 32e7a962c373f9e8b0a538b50ef9d2c2bd3bb23e Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 30 Jun 2016 10:41:04 -0700 Subject: [PATCH] Write fence.i before dret. Makes things work if the ROM doesn't contain fence.i (which is slow, so Andrew took it out). --- src/target/riscv/opcodes.h | 10 +++++----- src/target/riscv/riscv.c | 5 +++-- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/target/riscv/opcodes.h b/src/target/riscv/opcodes.h index 80d834475..935d91d0a 100644 --- a/src/target/riscv/opcodes.h +++ b/src/target/riscv/opcodes.h @@ -116,6 +116,11 @@ static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset) static uint32_t ebreak(void) { return MATCH_EBREAK; } static uint32_t ebreak_c(void) { return MATCH_C_EBREAK; } +static uint32_t fence_i(void) +{ + return MATCH_FENCE_I; +} + /* static uint32_t lui(unsigned int dest, uint32_t imm) { @@ -135,11 +140,6 @@ static uint32_t li(unsigned int dest, uint16_t imm) return addi(dest, 0, imm); } -static uint32_t fence_i(void) -{ - return MATCH_FENCE_I; -} - static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset) { return (bits(offset, 11, 5) << 25) | diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index d9b8ee380..7e75d4bfd 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -786,7 +786,8 @@ static int resume(struct target *target, int current, uint32_t address, dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false); dram_write32(target, 1, csrw(S0, CSR_DCSR), false); - dram_write_jump(target, 2, false); + dram_write32(target, 2, fence_i(), false); + dram_write_jump(target, 3, false); // Write DCSR value, set interrupt and clear haltnot. uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr; @@ -1016,10 +1017,10 @@ static int riscv_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE); - // Hardware single step doesn't exist yet. #if 1 return resume(target, current, address, handle_breakpoints, 0, true); #else + // Hardware single step doesn't exist yet. riscv_info_t *info = (riscv_info_t *) target->arch_info; uint32_t next_pc = info->dpc + 4; // TODO: write better next pc prediction code