Get rid of abort() calls.
Also changed a few asserts that could trigger due to broken hardware. Fixes Issue #142. Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
This commit is contained in:
Tim Newsome
parent
d7ed191457
commit
365c79c3ff
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@ -55,7 +55,6 @@ int riscv_program_exec(struct riscv_program *p, struct target *t)
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LOG_ERROR("Unable to write ebreak");
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for (size_t i = 0; i < riscv_debug_buffer_size(p->target); ++i)
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LOG_ERROR("ram[%02x]: DASM(0x%08lx) [0x%08lx]", (int)i, (long)p->debug_buffer[i], (long)p->debug_buffer[i]);
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abort();
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return ERROR_FAIL;
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}
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@ -152,7 +151,7 @@ int riscv_program_insert(struct riscv_program *p, riscv_insn_t i)
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LOG_ERROR("Unable to insert instruction:");
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LOG_ERROR(" instruction_count=%d", (int)p->instruction_count);
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LOG_ERROR(" buffer size =%d", (int)riscv_debug_buffer_size(p->target));
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abort();
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return ERROR_FAIL;
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}
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p->debug_buffer[p->instruction_count] = i;
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@ -1329,12 +1329,11 @@ static riscv_reg_t get_register(struct target *target, int hartid, int regid)
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return value;
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}
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static void set_register(struct target *target, int hartid, int regid,
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static int set_register(struct target *target, int hartid, int regid,
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uint64_t value)
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{
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assert(hartid == 0);
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/* TODO: propagate errors */
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register_write(target, regid, value);
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return register_write(target, regid, value);
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}
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static int halt(struct target *target)
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@ -31,22 +31,22 @@
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#define DMI_PROGBUF1 (DMI_PROGBUF0 + 1)
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static void riscv013_on_step_or_resume(struct target *target, bool step);
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static void riscv013_step_or_resume_current_hart(struct target *target, bool step);
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static int riscv013_step_or_resume_current_hart(struct target *target, bool step);
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static void riscv013_clear_abstract_error(struct target *target);
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/* Implementations of the functions in riscv_info_t. */
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static riscv_reg_t riscv013_get_register(struct target *target, int hartid, int regid);
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static void riscv013_set_register(struct target *target, int hartid, int regid, uint64_t value);
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static int riscv013_set_register(struct target *target, int hartid, int regid, uint64_t value);
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static void riscv013_select_current_hart(struct target *target);
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static void riscv013_halt_current_hart(struct target *target);
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static void riscv013_resume_current_hart(struct target *target);
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static void riscv013_step_current_hart(struct target *target);
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static int riscv013_halt_current_hart(struct target *target);
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static int riscv013_resume_current_hart(struct target *target);
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static int riscv013_step_current_hart(struct target *target);
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static void riscv013_on_halt(struct target *target);
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static void riscv013_on_step(struct target *target);
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static void riscv013_on_resume(struct target *target);
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static bool riscv013_is_halted(struct target *target);
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static enum riscv_halt_reason riscv013_halt_reason(struct target *target);
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static void riscv013_write_debug_buffer(struct target *target, unsigned index,
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static int riscv013_write_debug_buffer(struct target *target, unsigned index,
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riscv_insn_t d);
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static riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned
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index);
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@ -418,7 +418,7 @@ static uint64_t dmi_read(struct target *target, uint16_t address)
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if (status != DMI_STATUS_SUCCESS) {
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LOG_ERROR("Failed read from 0x%x; status=%d", address, status);
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abort();
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return ~0ULL;
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}
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/* This second loop ensures that we got the read
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@ -441,13 +441,13 @@ static uint64_t dmi_read(struct target *target, uint16_t address)
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if (status != DMI_STATUS_SUCCESS) {
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LOG_ERROR("Failed read (NOP) from 0x%x; value=0x%" PRIx64 ", status=%d",
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address, value, status);
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abort();
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return ~0ULL;
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}
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return value;
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}
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static void dmi_write(struct target *target, uint16_t address, uint64_t value)
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static int dmi_write(struct target *target, uint16_t address, uint64_t value)
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{
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select_dmi(target);
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dmi_status_t status = DMI_STATUS_BUSY;
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@ -470,7 +470,7 @@ static void dmi_write(struct target *target, uint16_t address, uint64_t value)
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if (status != DMI_STATUS_SUCCESS) {
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LOG_ERROR("Failed write to 0x%x;, status=%d",
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address, status);
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abort();
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return ERROR_FAIL;
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}
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/* The second loop isn't strictly necessary, but would ensure that the
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@ -490,8 +490,10 @@ static void dmi_write(struct target *target, uint16_t address, uint64_t value)
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}
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if (status != DMI_STATUS_SUCCESS) {
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LOG_ERROR("failed to write (NOP) 0x%" PRIx64 " to 0x%x; status=%d", value, address, status);
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abort();
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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static void increase_ac_busy_delay(struct target *target)
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@ -964,7 +966,7 @@ static int register_write_direct(struct target *target, unsigned number,
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riscv_program_csrw(&program, S0, number);
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} else {
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LOG_ERROR("Unsupported register (enum gdb_regno)(%d)", number);
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abort();
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return ERROR_FAIL;
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}
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}
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@ -1024,7 +1026,7 @@ static int register_read_direct(struct target *target, uint64_t *value, uint32_t
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riscv_program_csrr(&program, S0, number);
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} else {
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LOG_ERROR("Unsupported register (enum gdb_regno)(%d)", number);
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abort();
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return ERROR_FAIL;
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}
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/* Execute program. */
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@ -1885,7 +1887,7 @@ static riscv_reg_t riscv013_get_register(struct target *target, int hid, int rid
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return out;
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}
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static void riscv013_set_register(struct target *target, int hid, int rid, uint64_t value)
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static int riscv013_set_register(struct target *target, int hid, int rid, uint64_t value)
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{
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LOG_DEBUG("writing 0x%" PRIx64 " to register %s on hart %d", value,
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gdb_regno_name(rid), hid);
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@ -1893,22 +1895,28 @@ static void riscv013_set_register(struct target *target, int hid, int rid, uint6
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riscv_set_current_hartid(target, hid);
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if (rid <= GDB_REGNO_XPR31) {
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register_write_direct(target, rid, value);
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return register_write_direct(target, rid, value);
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} else if (rid == GDB_REGNO_PC) {
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LOG_DEBUG("writing PC to DPC: 0x%016" PRIx64, value);
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register_write_direct(target, GDB_REGNO_DPC, value);
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uint64_t actual_value;
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register_read_direct(target, &actual_value, GDB_REGNO_DPC);
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LOG_DEBUG(" actual DPC written: 0x%016" PRIx64, actual_value);
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assert(value == actual_value);
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if (value != actual_value) {
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LOG_ERROR("Written PC (0x%" PRIx64 ") does not match read back "
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"value (0x%" PRIx64 ")", value, actual_value);
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return ERROR_FAIL;
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}
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} else if (rid == GDB_REGNO_PRIV) {
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uint64_t dcsr;
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register_read_direct(target, &dcsr, GDB_REGNO_DCSR);
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dcsr = set_field(dcsr, CSR_DCSR_PRV, value);
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register_write_direct(target, GDB_REGNO_DCSR, dcsr);
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return register_write_direct(target, GDB_REGNO_DCSR, dcsr);
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} else {
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register_write_direct(target, rid, value);
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return register_write_direct(target, rid, value);
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}
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return ERROR_OK;
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}
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static void riscv013_select_current_hart(struct target *target)
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@ -1920,11 +1928,12 @@ static void riscv013_select_current_hart(struct target *target)
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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}
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static void riscv013_halt_current_hart(struct target *target)
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static int riscv013_halt_current_hart(struct target *target)
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{
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RISCV_INFO(r);
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LOG_DEBUG("halting hart %d", r->current_hartid);
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assert(!riscv_is_halted(target));
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if (riscv_is_halted(target))
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LOG_ERROR("Hart %d is already halted!", r->current_hartid);
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/* Issue the halt command, and then wait for the current hart to halt. */
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uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
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@ -1941,19 +1950,21 @@ static void riscv013_halt_current_hart(struct target *target)
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LOG_ERROR("unable to halt hart %d", r->current_hartid);
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LOG_ERROR(" dmcontrol=0x%08x", dmcontrol);
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LOG_ERROR(" dmstatus =0x%08x", dmstatus);
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abort();
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return ERROR_FAIL;
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}
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dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 0);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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return ERROR_OK;
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}
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static void riscv013_resume_current_hart(struct target *target)
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static int riscv013_resume_current_hart(struct target *target)
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{
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return riscv013_step_or_resume_current_hart(target, false);
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}
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static void riscv013_step_current_hart(struct target *target)
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static int riscv013_step_current_hart(struct target *target)
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{
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return riscv013_step_or_resume_current_hart(target, true);
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}
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@ -1998,10 +2009,10 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
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LOG_ERROR("Unknown DCSR cause field: %x", (int)get_field(dcsr, CSR_DCSR_CAUSE));
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LOG_ERROR(" dcsr=0x%016lx", (long)dcsr);
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abort();
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return RISCV_HALT_UNKNOWN;
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}
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void riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_insn_t data)
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int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_insn_t data)
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{
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return dmi_write(target, DMI_PROGBUF0 + index, data);
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}
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@ -2070,17 +2081,20 @@ static void riscv013_on_step_or_resume(struct target *target, bool step)
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riscv_set_register(target, GDB_REGNO_DCSR, dcsr);
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}
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static void riscv013_step_or_resume_current_hart(struct target *target, bool step)
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static int riscv013_step_or_resume_current_hart(struct target *target, bool step)
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{
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RISCV_INFO(r);
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LOG_DEBUG("resuming hart %d (for step?=%d)", r->current_hartid, step);
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assert(riscv_is_halted(target));
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if (!riscv_is_halted(target)) {
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LOG_ERROR("Hart %d is not halted!", r->current_hartid);
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return ERROR_FAIL;
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}
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struct riscv_program program;
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riscv_program_init(&program, target);
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riscv_program_fence_i(&program);
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if (riscv_program_exec(&program, target) != ERROR_OK)
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abort();
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return ERROR_FAIL;
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/* Issue the resume command, and then wait for the current hart to resume. */
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uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
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@ -2097,7 +2111,7 @@ static void riscv013_step_or_resume_current_hart(struct target *target, bool ste
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dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ, 0);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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return;
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return ERROR_OK;
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}
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uint32_t dmstatus = dmi_read(target, DMI_DMSTATUS);
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@ -2109,10 +2123,10 @@ static void riscv013_step_or_resume_current_hart(struct target *target, bool ste
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if (step) {
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LOG_ERROR(" was stepping, halting");
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riscv013_halt_current_hart(target);
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return;
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return ERROR_OK;
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}
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abort();
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return ERROR_FAIL;
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}
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void riscv013_clear_abstract_error(struct target *target)
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@ -1011,6 +1011,9 @@ int riscv_openocd_poll(struct target *target)
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case RISCV_HALT_SINGLESTEP:
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target->debug_reason = DBG_REASON_SINGLESTEP;
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break;
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case RISCV_HALT_UNKNOWN:
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target->debug_reason = DBG_REASON_UNDEFINED;
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break;
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}
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if (riscv_rtos_enabled(target)) {
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@ -1361,8 +1364,7 @@ int riscv_halt_one_hart(struct target *target, int hartid)
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return ERROR_OK;
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}
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r->halt_current_hart(target);
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return ERROR_OK;
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return r->halt_current_hart(target);
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}
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int riscv_resume_all_harts(struct target *target)
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@ -1389,8 +1391,7 @@ int riscv_resume_one_hart(struct target *target, int hartid)
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}
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r->on_resume(target);
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r->resume_current_hart(target);
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return ERROR_OK;
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return r->resume_current_hart(target);
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}
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int riscv_step_rtos_hart(struct target *target)
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@ -1407,13 +1408,20 @@ int riscv_step_rtos_hart(struct target *target)
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riscv_set_current_hartid(target, hartid);
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LOG_DEBUG("stepping hart %d", hartid);
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assert(riscv_is_halted(target));
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if (!riscv_is_halted(target)) {
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LOG_ERROR("Hart isn't halted before single step!");
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return ERROR_FAIL;
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}
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riscv_invalidate_register_cache(target);
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r->on_step(target);
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r->step_current_hart(target);
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if (r->step_current_hart(target) != ERROR_OK)
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return ERROR_FAIL;
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riscv_invalidate_register_cache(target);
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r->on_halt(target);
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assert(riscv_is_halted(target));
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if (!riscv_is_halted(target)) {
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LOG_ERROR("Hart was not halted after single step!");
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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@ -1523,13 +1531,12 @@ bool riscv_has_register(struct target *target, int hartid, int regid)
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return 1;
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}
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void riscv_set_register(struct target *target, enum gdb_regno r, riscv_reg_t v)
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int riscv_set_register(struct target *target, enum gdb_regno r, riscv_reg_t v)
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{
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/* TODO: propagate errors */
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return riscv_set_register_on_hart(target, riscv_current_hartid(target), r, v);
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}
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void riscv_set_register_on_hart(struct target *target, int hartid,
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int riscv_set_register_on_hart(struct target *target, int hartid,
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enum gdb_regno regid, uint64_t value)
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{
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RISCV_INFO(r);
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@ -1562,7 +1569,10 @@ enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
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{
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RISCV_INFO(r);
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riscv_set_current_hartid(target, hartid);
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assert(riscv_is_halted(target));
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if (!riscv_is_halted(target)) {
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LOG_ERROR("Hart is not halted!");
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return RISCV_HALT_UNKNOWN;
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}
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return r->halt_reason(target);
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}
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@ -30,6 +30,7 @@ enum riscv_halt_reason {
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RISCV_HALT_INTERRUPT,
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RISCV_HALT_BREAKPOINT,
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RISCV_HALT_SINGLESTEP,
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RISCV_HALT_UNKNOWN
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};
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typedef struct {
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@ -88,18 +89,18 @@ typedef struct {
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/* Helper functions that target the various RISC-V debug spec
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* implementations. */
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riscv_reg_t (*get_register)(struct target *, int hartid, int regid);
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void (*set_register)(struct target *, int hartid, int regid,
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int (*set_register)(struct target *, int hartid, int regid,
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uint64_t value);
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void (*select_current_hart)(struct target *);
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bool (*is_halted)(struct target *target);
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void (*halt_current_hart)(struct target *);
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void (*resume_current_hart)(struct target *target);
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void (*step_current_hart)(struct target *target);
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int (*halt_current_hart)(struct target *);
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int (*resume_current_hart)(struct target *target);
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int (*step_current_hart)(struct target *target);
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void (*on_halt)(struct target *target);
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void (*on_resume)(struct target *target);
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void (*on_step)(struct target *target);
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enum riscv_halt_reason (*halt_reason)(struct target *target);
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void (*write_debug_buffer)(struct target *target, unsigned index,
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int (*write_debug_buffer)(struct target *target, unsigned index,
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riscv_insn_t d);
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riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
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int (*execute_debug_buffer)(struct target *target);
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@ -202,8 +203,8 @@ bool riscv_has_register(struct target *target, int hartid, int regid);
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/* Returns the value of the given register on the given hart. 32-bit registers
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* are zero extended to 64 bits. */
|
||||
void riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
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||||
void riscv_set_register_on_hart(struct target *target, int hid, enum gdb_regno rid, uint64_t v);
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||||
int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
|
||||
int riscv_set_register_on_hart(struct target *target, int hid, enum gdb_regno rid, uint64_t v);
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||||
riscv_reg_t riscv_get_register(struct target *target, enum gdb_regno i);
|
||||
riscv_reg_t riscv_get_register_on_hart(struct target *target, int hid, enum gdb_regno rid);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue